CMOS inverter-based voltage and current references in short channel technologies

2014 ◽  
Author(s):  
K. R. Raghunandan ◽  
T. R. Viswanathan
Keyword(s):  
Cmos Inverter ◽  
Short Channel

HIGHLY SCALED CMOS DEVICE TECHNOLOGIES WITH NEW STRUCTURES AND NEW MATERIALS

2006 ◽  
Vol 16 (01) ◽  
pp. 147-173
Author(s):  
YANGYUAN WANG ◽  
RU HUANG ◽  
JINFENG KANG ◽  
SHENGDONG ZHANG
Keyword(s):  
Field Effect Transistors ◽  
Silicon Film ◽  
Double Gate ◽  
New Materials ◽  
Metal Gate ◽  
Gate Stack ◽  
Cmos Inverter ◽  
Short Channel ◽  
High K ◽  
Dual Metal

In this paper field effect transistors (FETs) with new materials and new structures are discussed. A thermal robust HfN/HfO 2 gate stack, which can alleviate the confliction between high quality high k material and low EOT, is investigated. EOT of the gate stack can be scaled down to 0.65nm for MOS capacitor and 0.95nm for MOSFET with higher carrier mobility. A new dual metal gate/high k CMOS integration process was demonstrated based on a dummy HfN technique for better high k quality and metal gate integration. Several new double gate FETs are proposed and investigated, including vertical double gate device with an asymmetric graded lightly doped drain (AGLDD) for better short channel behavior, self-aligned electrically separable double gate device for dynamic threshold voltage operation, new 3-D CMOS inverter based on double gate structure and SOI substrate for compact configuration and new full-symmetric DGJFET for 10nm era with greatly relaxed requirement of silicon film thickness and device design simplification.

scholarly journals Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor

2021 ◽  
Vol 10 (6) ◽  
pp. 1-10
Author(s):  
S.C. Wagaj ◽  
◽  
S.C. Patil ◽  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Silicon On Insulator ◽  
Cmos Circuits ◽  
Gate Stack ◽  
Cmos Inverter ◽  
Short Channel ◽  
Junctionless Transistor ◽  
Dual Gate ◽  
Static Power

In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves the short channel effect but also improve the performance of CMOS circuits of this device. The proposed device shielded channel dual gate stack silicon on nothing junctionless transistor (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved by 20%, 39% and 20% respectively over the single material gate silicon on insulator junctionless transistor (SMG SOI JLT). The proposed device CMOS inverter fall time Tf (pS) and noise margin improves by 50% and 10% compare to shielded channel silicon on insulator junctionless transistor (SCSOIJLT). It has been observed that circuit simulation of CMOS inverter, NAND and NOR of proposed device. The static power dissipation in the case of proposed SCDGSSONJLT device are reduced by 45%, 81% and 83% respectively over the SMGSOIJLT. Thus, significant improvement in DIBL, cut-off frequency, propagation delay and static power dissipation at low power supply voltage shows that the proposed device is more suitable for low power CMOS circuits.

scholarly journals Modelling, Design, and Performance Comparison of Triple Gate Cylindrical and Partially Cylindrical FinFETs for Low-Power Applications

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Sanjeev Rai ◽  
Jyotsna Sahu ◽  
Wanjul Dattatray ◽  
R. A. Mishra ◽  
Sudarshan Tiwari
Keyword(s):  
Side Wall ◽  
Propagation Delay ◽  
Performance Comparison ◽  
Cmos Inverter ◽  
Short Channel ◽  
Wall Area ◽  
Region I ◽  
Channel Effects ◽  
In Series ◽  
And Performance

The FinFETs recently have been the rallying point for the engineers as far as the development of the technology is concerned. The authors here have tried successfully to compare the performance of 30 nm conventional triple gate (Conv) FinFET structure with that of partially cylindrical (PC) FinFET. In PC-FinFET the fin is divided into two regions. Region I is partially cylindrical and has curvature of half of the fin width, and Region II is like a conventional FinFET (having flat region). The results show that there is considerable improvement in Ion, Ioff, and subsequent suppression of short channel effects, that is, subthreshold slope, DIBL, self heating effect, and so forth. The improvement has also been felt in series resistance in PC-FinFET as compared to C-FinFET. It is noteworthy also to mention that in PC-FinFET the corner of fin is rounded thus reducing the side wall area which further reduces the gate capacitance reducing the intrinsic delay. The DC and transient analysis of CMOS inverter using C-FinFET and PC-FinFET have been done which shows that PC-FinFET inverter has reduced propagation delay as compared to C-FinFET.

scholarly journals p-Type Trigate Junctionless Nanosheet MOSFET: Analog/RF, Linearity, and Circuit Analysis

2021 ◽  
Author(s):  
Bharath Sreenivasulu Vakkalakula ◽  
Narendar Vadthiya
Keyword(s):  
High Performance ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Power Performance ◽  
Cmos Inverter ◽  
Short Channel ◽  
Future Technology ◽  
Road Map ◽  
P Type ◽  
Technology Nodes

Abstract Silicon (Si) nanosheet (NS) metal-oxide semiconductor field effect transistors (MOSFETs) are realized as an outstanding structure to obtain better area scaling and power performance compared to FinFETs. Si NS MOSFETs provide high current drivability due to wider effective channel (Weff) and maintain better short channel performance. Here, the performance of junctionless (JL) NS p-MOSFET was evaluated by invoking HfxTi1-xO2 gate stack. The device performance was enhanced using various spacer dielectrics and the electrical characteristics are presented. Moreover, the effect of NS width variation on ION/IOFF, SS, Vth is presented and the analog/RF metrics of the device are evaluated. The power analysis of NS MOSFET is presented with respect to the ITRS road map. Our investigation reveals that the device exhibits an ION/IOFF ratio of more than ~106 with NS widths of 10 to 30 nm, respectively. For high-performance applications, the device exhibits better performance (ION) with higher NS widths. However, the threshold voltage downfall leads to deterioration in subthreshold performance with an increase in NS widths. With Si3N4 as a spacer dielectric the device exhibits better static power consumption for the CMOS inverter. By careful control of NS width and effective usage of spacer dielectric ensures better p-MOSFET design for future technology nodes.

Monte Carlo study of 50 nm-long single and dual-gate MODFETs: suppression of short-channel effects

1993 ◽  
Vol 3 (9) ◽  
pp. 1719-1728
Author(s):  
P. Dollfus ◽  
P. Hesto ◽  
S. Galdin ◽  
C. Brisset
Keyword(s):  
Monte Carlo ◽  
Monte Carlo Study ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
Dual Gate

A NEW PUNCHTHROUGH MODEL FOR SHORT CHANNEL MOSFET

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-761-C4-764
Author(s):  
D. CHEN ◽  
Z. LI
Keyword(s):  
Short Channel

Short Channel Poly-Si TFT with Single Grain Boundary by Excimer Laser Annealing on Al-masked a-Si Layer

2002 ◽  
Vol 715 ◽  
Author(s):  
Sang-Hoon Jung ◽  
Jae-Hoon Lee ◽  
Min-Koo Han
Keyword(s):  
Grain Boundary ◽  
Laser Annealing ◽  
Thin Film Transistor ◽  
High Mobility ◽  
Silicon Layer ◽  
Silicon Thin Film ◽  
Short Channel ◽  
Excimer Laser Annealing ◽  
Boundary Density ◽  
Single Grain

AbstractA short channel polycrystalline silicon thin film transistor (poly-Si TFT), which has single grain boundary in the center of channel, is reported. The reported poly-Si TFT employs lateral grain growth method through aluminum patterns, which acts as a selective beam mask and a lateral heat sink during the laser irradiation, on an amorphous silicon layer. The electrical characteristics of the proposed poly-Si TFT have been considerably improved due to grain boundary density lowered. The reported short channel poly-Si TFT with single grain boundary exhibits high mobility as 222 cm2/Vsec and large on/off current ratio exceeding 1 × 108.

Co-planar two-dimensional Metal-Insulator-Semiconductor Capacitor: Numerical study of the device electrostatics.

2017 ◽  
Author(s):  
Varun Bheemireddy
Keyword(s):  
Space Charge ◽  
High Performance ◽  
Numerical Study ◽  
2D Materials ◽  
Space Charge Density ◽  
Two Dimensional ◽  
Short Channel ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
New Family

The two-dimensional(2D) materials are highly promising candidates to realise elegant and e cient transistor. In the present letter, we conjecture a novel co-planar metal-insulator-semiconductor(MIS) device(capacitor) completely based on lateral 2D materials architecture and perform numerical study of the capacitor with a particular emphasis on its di erences with the conventional 3D MIS electrostatics. The space-charge density features a long charge-tail extending into the bulk of the semiconductor as opposed to the rapid decay in 3D capacitor. Equivalently, total space-charge and semiconductor capacitance densities are atleast an order of magnitude more in 2D semiconductor. In contrast to the bulk capacitor, expansion of maximum depletion width in 2D semiconductor is observed with increasing doping concentration due to lower electrostatic screening. The heuristic approach of performance analysis(2D vs 3D) for digital-logic transistor suggest higher ON-OFF current ratio in the long-channel limit even without third dimension and considerable room to maximise the performance of short-channel transistor. The present results could potentially trigger the exploration of new family of co-planar at transistors that could play a signi significant role in the future low-power and/or high performance electronics.<br>

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