RFICs packages electrical performance comparison of both ULTRA-CSP and Standard TSOP

Author(s):  
T. Hsu ◽  
K. Chiang ◽  
Yu-Po Wang
Materials ◽  
2021 ◽  
Vol 14 (7) ◽  
pp. 1684
Author(s):  
Farah Asyikin Abd Rahman ◽  
Mohd Zainal Abidin Ab Kadir ◽  
Ungku Anisa Ungku Amirulddin ◽  
Miszaina Osman

The fourth rail transit is an interesting topic to be shared and accessed by the community within that area of expertise. Several ongoing works are currently being conducted especially in the aspects of system technical performances including the rail bracket component and the sensitivity analyses on the various rail designs. Furthermore, the lightning surge study on railway electrification is significant due to the fact that only a handful of publications are available in this regard, especially on the fourth rail transit. For this reason, this paper presents a study on the electrical performance of a fourth rail Direct Current (DC) urban transit affected by an indirect lightning strike. The indirect lightning strike was modelled by means of the Rusck model and the sum of two Heidler functions. The simulations were carried out using the EMTP-RV software which included the performance comparison of polymer-insulated rail brackets, namely the Cast Epoxy (CE), the Cycloaliphatic Epoxy A (CEA), and the Glass Reinforced Plastic (GRP) together with the station arresters when subjected by 30 kA (5/80 µs) and 90 kA (9/200 µs) lightning currents. The results obtained demonstrated that the GRP material has been able to slightly lower its induced overvoltage as compared to other materials, especially for the case of 90 kA (9/200 µs), and thus serves better coordination with the station arresters. This improvement has also reflected on the recorded residual voltage and energy absorption capacity of the arrester, respectively.


2015 ◽  
Vol 645-646 ◽  
pp. 1024-1031
Author(s):  
Zhen Song Li ◽  
Min Miao ◽  
Shao Chun Yang ◽  
Da Cheng Yang

A novel Bar TSV(B-TSV) structure, formed by two semi-cylinders combining with a quadrangular is studied in this paper. This B-TSV structure extends the TSV design options by introducing new design parameters. The scalable electrical model of B-TSV is proposed and the effects of design parameters, such as the side length of quadrangular and the minimum distance between TSVs are investigated and concluded by a 3D electromagnetic solver. Performance comparison between B-TSV and the traditional cylindrical one is also provided by simulation under the Ground-Signal-Ground configuration. Simulation results show that B-TSV has better performance than the traditional one, and can be used to increase the TSV array density without degrading the electrical performance of TSV system.


2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Johanna Virkki ◽  
Zhigang Wei ◽  
Aruhan Liu ◽  
Leena Ukkonen ◽  
Toni Björninen

We present a wearable passive UHF RFID tag based on a slotted patch antenna comprising only textile materials (e-textile, textile substrate, and conductive yearn). As a novel manufacturing approach, we realize the patch-to-ground and antenna-to-IC interfaces using only conductive thread and a sewing machine. We outline the electromagnetic optimization of the antenna for body-worn operation through simulations and present a performance comparison between the e-textile tag and a tag produced using regular electronics materials and methods. The measured results show that the textile tag achieves the electrical performance required in practical applications and that the slotted patch type antenna provides stable electromagnetic performance in different body-worn configurations.


Author(s):  
Bryan Hsieh ◽  
Kevin Chiang ◽  
Y. P. Wang ◽  
C. S. Hsiao

The memory storage technology revolution has taken the consumer electronics by a storm in just two years. The volatile memory Dynamic Random Access Memory (DRAM) for PC and notebook computing and gaming are increasing in density and speed. With all these improvement, the memory device packaging technology is also evolving rapidly, from the leadframe packages to BGA packages [2]. Under high frequency operation, the parasitics associated with package will significantly degrade the package performance. The DRAM packages are used primarily in the fabrication of DIMM modules that are inserted to the motherboards in PC and notebook computers. With newer DRAM technology in double date rate (DDR) and its second generation, DDR2, to be deployed just two years, it has higher clock rate and I/O number. Packages therefore are changing form the leadframe TSOP type 2 to faster CSPs such as fine pitch BGA (FBGA) and chip on substrate BGA (COSBGA). This paper is focused the COSBGA package [3,4]. In this paper, the packages electrical model have been established and performs signal integrity (SI) simulation. The COSBGA has smallest parasitics when comparison with other two packages. This paper also compares the performance of the COSBGA, TFBGA and TSOPII from crosstalk noise, time skew, insertion loss and return loss for IC designer reference.


Author(s):  
Anton Riley ◽  
Sean Zumwalt ◽  
Sinjin Dixon-Warren ◽  
Gary Tomkins

Abstract In today’s competitive semiconductor environment, product performance and market timing has never been more valuable. Design IP, speed to market, and taking advantage of the most advanced technology are three ways fabless companies can maintain an advantage over the competition. Foundries target these demands by offering superior support, competitive technology, and rapid development cycles. Using the advanced tool suites of SEM, FIB, TEM, and Atomic Force NanoProbing (AFP) the failure analysis community now has the ability to investigate and compare foundry performance on the device level. The 28 nm LP Qualcomm “SHELBY” die is dual-sourced from both Samsung and TSMC, and is the primary die in the MDM9215 4G/LTE modem used in several smartphones. This represents a unique case of leading technology, available to the public, to qualify for electrical performance on the device level using the AFP and the corresponding physical differences using SEM and TEM. These advanced FA techniques were employed and were able to identify manufacturing differences between foundries. They were then used to relate the physical variations with the electrical device performance. The HG11-N3877 fabricated by TSMC and the HG11-N9204 fabricated by Samsung were the subjects of this comparison (see Error! Reference source not found.). The investigation located spatial and geometric variations of the SRAM devices using cross sectioning and TEM imaging. This was followed by Electrical Characterization of multiple SRAM Cells using the AFP. The electrical measurements showed clear differences in device parameters. These differences highlight manufacturing process differences between the two companies that could directly relate to chip performance.


Author(s):  
Kunal Sandip Garud ◽  
Mahesh Suresh Patil ◽  
Jae-Hyeong Seo ◽  
You-Ma Bang ◽  
Chong-Pyo Cho ◽  
...  

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