Numerical study on wafer level warpage evolution during chip to wafer hybrid bonding process

Rising demand in memory is just one example how 3D integration is still gaining momentum. Not only the form factor but also performance is improved for several 3D integration applications by reducing the wafer thickness. Two competing process flows using thin wafers are to carry out for 3D integration today. Firstly, two wafers can be bonded face-to-face with subsequent thinning without the need to handle a thin wafer. However, some chip designs require a face-to-back stacking of thin wafers, where temporary bonding becomes an inevitable process step. In this case, the challenge of the temporary bonding process is different to traditional stacking on chip level, where usually the wafers are diced after debonding and then stacked on chip level, which means die thicknesses are typically in the range of 50 μm. The goal of wafer level transfer is a massive reduction of the wafer thickness. Therefore temporary and permanent bonding has to be combined to enable stacking on wafer level with very thin wafers. The first step is temporary bonding of the device wafer with the temporary carrier through an adhesive interlayer, followed by thinning and other backside processes. Afterwards the thinned wafer is permanently bonded to the target wafer before debonding from the carrier wafer. This can be repeated several times to be suitable for example a high bandwidth memory, where several layers of DRAM are stacked on top of each other. Another application is the memory integration on processors, or die segmentation processes. The temporary bonding process flow has to be very well controlled in terms of total thickness variations (TTV) of the intermediate adhesive between device and carrier wafer. The requirements for the temporary bonding adhesive include offering sufficient adhesion between device and carrier wafer for the subsequent processes. The choice of the material class for this study is the Brewer Science dual layer material comprising of a curable layer which offers high mechanical stability to enable low TTV during the thinning process and a release layer for mechanical debond process. The release layer must lead to a successful debond but prevent spontaneous debonding during grinding and other processes. Total thickness variation values of the adhesive will be analyzed in dependence of the adhesive layer thickness as this is a key criterion for a successful implementation at the manufactures. Besides the TTV the mechanical stability during grinding will be evaluated by CSAM to make sure no delamination has happened. For feasibility of the total process flow it is important that the mechanical debonding requires less force compared to the separation of the permanent bonded wafers. Other process parameters such as edge trimming of the device wafer as well as edge removal of the mechanical debond release layer are investigated.

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Characterization of Wafer Level Metal Thermo-Compression Bonding

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2010dpc-tha34 ◽

2010 ◽

Vol 2010 (DPC) ◽

pp. 002326-002360

Author(s):

Erkan Cakmak ◽

Bioh Kim ◽

Viorel Dragoi

Keyword(s):

Surface Treatment ◽

Metal Surface ◽

Bonding Temperature ◽

Transient Liquid Phase ◽

Bonding Process ◽

Bending Test ◽

Strength Analysis ◽

Mems Devices ◽

Wafer Level ◽

Bond Quality

The process of wafer-level bonding is being successfully used to form MEMS devices. Wafer level bonding may be realized by different methods such as thermo compression, transient liquid phase, anodic, glass frit, or polymer bonding. These methods have different requirements and the choice of wafer level bonding method is defined by the application type. Metal TCB has a wide variety of applications with materials of choice including Au, Cu and Al. 3D electrical connections are created by the use of Cu-Cu TCB; while CMOS MEMS devices may be realized by Al-Al TCB. In this study the wafer level bonding process of Cu-Cu and Al-Al TCB are characterized. The effects and significance of various bonding process parameters and surface treatment methods are reported on the final bond interfaces integrity and strength. Analysis methods include SAM, SEM, AFM, and four point bending test. Al-Al TCB samples were investigated on the interfacial adhesion energy and bond quality. IAE and bond quality were found to be positively correlated with bonding temperature. A bonding temperature of 500 °C or greater is necessary to obtain bond strengths of 8–10 J/m2. A positive relation between IAE and bonding temperature was observed for Cu-Cu TCB. IAE's of greater then 10 J/m2 were obtained on bonded samples that do not show a post bond residual seam on the bonding interface. An acid based pre treatment was shown to impact the surface properties of the initial metal surface hence affecting the IAE. Post bond annealing processes showed the most significant impact on the IAE of the Cu-Cu TCB system. To obtain comparable IAE values the Al-Al TCB method requires a higher bonding temperature. However the Cu-Cu TCB is sensitive to the initial metal surface condition and requires surface treatment processes prior to bonding to obtain high quality bonding results.

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Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2015dpc-tp31 ◽

2015 ◽

Vol 2015 (DPC) ◽

pp. 000698-000725 ◽

Cited By ~ 1

Author(s):

Kai Zoschke ◽

Klaus-Dieter Lang

Keyword(s):

Wafer Bonding ◽

Rf Mems ◽

Electrical Contacts ◽

Bonding Process ◽

Frame Structure ◽

Back Side ◽

Wafer Level ◽

Free Standing ◽

Carrier Wafer ◽

Base Substrate

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general. The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages. However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways. The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap. The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail. All processes were performed at 200mm wafer level.

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A numerical study on mitigation of flying dies in compression molding of microelectronic packages

International Symposium on Microelectronics ◽

10.4071/2380-4505-2018.1.000355 ◽

2018 ◽

Vol 2018 (1) ◽

pp. 000355-000360

Author(s):

Marc Dreissigacker ◽

Ole Hoelck ◽

Joerg Bauer ◽

Tanja Braun ◽

Karl-Friedrich Becker ◽

...

Keyword(s):

Numerical Study ◽

Compression Molding ◽

Packaging Material ◽

Process Conditions ◽

Microelectronic Packaging ◽

Wafer Level ◽

Temperature Dependent ◽

Wafer Level Packaging ◽

Compression Speed ◽

Complex Manner

Abstract Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds (EMC) depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity. The focus is set on forces exerted on individual dies during encapsulation in Fan-Out Wafer Level Packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemo-rheology, as well as to extract forces exerted on individual dies. It offers separate evaluation of pressure and shear-contributions for two cases, 0 ° and 45 ° between the dies' frontal area and the melt front. Process parameters, such as compression speed and process temperature, are determined to minimize flying dies and thereby maximize yield. The approach is easily scalable and is therefore well suited to face the challenges that come with the current efforts towards the transition from FOWLP to FOPLP (Fan-Out Panel Level Packaging).

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Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2012dpc-wp13 ◽

2012 ◽

Vol 2012 (DPC) ◽

pp. 1-24

Author(s):

Michael Gallagher ◽

Jong-Uk Kim ◽

Eric Huenger ◽

Kai Zoschke ◽

Christina Lopper ◽

...

Keyword(s):

Low Temperature ◽

Wafer Bonding ◽

Flip Chip ◽

Bonding Temperature ◽

Bonding Process ◽

Curing Temperature ◽

Wafer Level ◽

Mechanical Adhesion ◽

3D Stacking ◽

Dry Etch

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state. Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

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Reliability and Characterization of Micro-Packages in a Wafer Level Au-Si Eutectic Vacuum Bonding Process

Advances in Electronic Packaging, Parts A, B, and C ◽

10.1115/ipack2005-73341 ◽

2005 ◽

Cited By ~ 2

Author(s):

Jay S. Mitchell ◽

Gholamhassan R. Lahiji ◽

Khalil Najafi

Keyword(s):

High Sensitivity ◽

Pressure Change ◽

Bonding Process ◽

Wafer Level ◽

Eutectic Solder ◽

Packaging Process ◽

Primary Mechanism ◽

Airtight Seal ◽

Over Time

A Au-Si eutectic vacuum packaging process was evaluated using high sensitivity poly-Si Pirani vacuum sensors. Encapsulation of devices was achieved by bonding a silicon cap wafer to a device wafer using a Au-Si eutectic solder at above 390°C in a vacuum bonder. The Au-Si eutectic solder encircled the devices, providing an airtight seal. The Pirani gauges were encapsulated and tested over a period of several months in order to determine base pressures and leak/outgassing rates of the micro-cavities. Packaged devices without getters showed initial pressures from 2 to 12 Torr with initial leak/outgassing rates of −0.073 to 80 Torr/year. Using getters, pressures as low as 5 mTorr have been achieved with leak/outgassing rates of <10 mTorr/year. Trends in pressure over time seem to indicate outgassing (desorption of atoms from inside of the microcavity) as the primary mechanism for pressure change over time.

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Research of Wafer Level Bonding Process Based on Cu–Sn Eutectic

Micromachines ◽

10.3390/mi11090789 ◽

2020 ◽

Vol 11 (9) ◽

pp. 789

Author(s):

Daowei Wu ◽

Wenchao Tian ◽

Chuqiao Wang ◽

Ruixia Huo ◽

Yongkun Wang

Keyword(s):

Oxide Layer ◽

Performance Indicators ◽

Metal Layer ◽

Bonding Process ◽

Wafer Surface ◽

Wafer Level ◽

Industry Standards ◽

Vertical Interconnection ◽

Pretreatment Conditions ◽

System Packaging

In 3D-system packaging technologies, eutectic bonding is the key technology of multilayer chip stacking and vertical interconnection. Optimized from the aspects of the thickness of the electroplated metal layer, the pretreatment of the wafer surface removes the oxide layer, the mutual alignment between the wafers, the temperature of the wafer bonding, the uniformity of pressure and the deviation of the bonding process. Under the pretreatment conditions of plasma treatment and citric acid cleaning, no oxide layer was obtained on the metal surface. Cu/Sn bumps bonded under the condition of 0.135 Mpa, temperature of 280 °C, Sn thickness of 3–4 μm and a Cu-thickness of five micrometers. Bonded push crystal strength ≥18 kg/cm2, the average contact resistance of the bonding interface is about 3.35 mΩ, and the bonding yield is 100%. All performance indicators meet and exceed the industry standards.

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