The Development of Semiconductor Packaging Industry in China

2006 ◽  
Author(s):  
Keyun Bi
Keyword(s):  
Packaging Industry ◽  
Semiconductor Packaging

Approaches for Measurement System Analysis Considering Randomness and Fuzziness

2020 ◽  
Vol 9 (2) ◽  
pp. 98-131
Author(s):  
Liang-Hsuan Chen ◽  
Chia-Jung Chang
Keyword(s):  
Measurement System ◽  
System Analysis ◽  
Sum Of Squares ◽  
Measurement System Analysis ◽  
Repeatability And Reproducibility ◽  
Packaging Industry ◽  
Relationship Of ◽  
Semiconductor Packaging ◽  
The Relationship ◽  
Fuzzy Random

For some quality inspection practices, subjective judgements based on the inspectors' experience and knowledge, such as visual inspection, may be required for some particular quality characteristics. This kind of measurement system, including its associated randomness and fuzziness, should be assessed by Measurement system analysis (MSA) before its application. For such purpose, this article represents observations with randomness and fuzziness from MSAs as fuzzy random variables, and then two pairs of descriptive parameters, i.e., expected value and variance, are derived. Then, the relationship of the total sum of squares of factors is proven to hold, so that fuzzy analysis of variance (FANOVA) in terms of gauge repeatability and reproducibility can be developed. The proposed approach has the advantage that FANOVA is developed based on the relationship of the total sum of squares of factors, considering randomness and fuzziness. A real case in the semiconductor packaging industry is used to demonstrate the applicability of the proposed approaches to MSA.

Wire Bond Shear Test Simulation on Sharp Groove Surface Bond Pad

2012 ◽  
Vol 622-623 ◽  
pp. 647-651 ◽  
Author(s):  
Z. Sauli ◽  
V. Retnasamy ◽  
S. Taniselass ◽  
A.H.M. Shapri ◽  
R. Vairavan
Keyword(s):  
Stress Response ◽  
Shear Test ◽  
Copper Wire ◽  
Gold Wire ◽  
Shear Tests ◽  
Groove Surface ◽  
Wire Bond ◽  
Packaging Industry ◽  
Semiconductor Packaging ◽  
Surface Bond

Wire bonding process is first level interconnection technology used in the semiconductor packaging industry. The wire bond shear tests are used in the industry to examine the bond strength and reliability of the bonded wires. Hence, in this study thesimulation on wire bond shear test is performed on a sharp groove surface bond pad. ANSYS ver 11 was used to perform the simulation. The stress response of the bonded wires are investigated.The effects of three wire materials gold(Au), aluminum(Al) and copper(Cu) on the stress response during shear test were examined. The simulation results showed that copper wire bond induces highest stress and gold wire exhibits the least stress response.

scholarly journals A Study of Vacuum Efficiency for Silicon on Insulator Wafers

2019 ◽  
pp. 1-6
Author(s):  
Bryan Christian S. Bacquian ◽  
Frederick Ray I. Gomez
Keyword(s):  
Integrated Circuit ◽  
Vertical Structure ◽  
Silicon On Insulator ◽  
Major Contributor ◽  
Ic Design ◽  
Packaging Industry ◽  
Ic Package ◽  
Semiconductor Packaging ◽  
Step Type ◽  
Soi Technology

The development on thinner packages has become the trend and focus in semiconductor packaging industry. The necessity of thinner packages also entails a thinner vertical structure of the integrated circuit (IC) design. As a major contributor on the vertical structure of the IC package, die or wafer is also essential to go thinner. As the wafer goes thinner, various problems may occur during transport and even the back grinding process, itself. Wafer warpage is one of the main concerns during the process. The effect of proper vacuuming will play major role in processing SOI wafers. Insufficient vacuum may cause non-planar wafer in contact with the chuck table that may result to poorer grinding and worst broken wafer.  Different silicon wafer technology has been released to cater different functionality on different industry markets. One popular silicon technology is Silicon On Insulator (SOI) technology. SOI wafers have a step type passivation wherein the edge of the wafer is observed to have 30um thinner than its center. The stepping effect also contributes to the 0.5mm wafer warpage prior back grinding. Evaluating the effect of vacuum efficiency to eliminate such warpage is discussed on this technical paper.

Development of No Flow Underfills for Lead-Free Flip Chip Applications

2006 ◽  
Author(s):  
Kaustubh Nagarkar ◽  
Tan Zhang ◽  
David Esler ◽  
David Simon ◽  
Paul Gillespie ◽  
...  
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Stencil Printing ◽  
Significant Research ◽  
Flip Chip Packaging ◽  
Chip Carrier ◽  
Packaging Industry ◽  
The Impact ◽  
Semiconductor Packaging ◽  
Underfill Material

Flip chip packaging is one of the fastest growing segments in electronics packaging technology. The semiconductor packaging industry is continuing to migrate towards Pb-free electronics assembly. Therefore, the development of compatible materials for Pb-free flip chip packaging is critical to this transition [1]. Flip chip devices are commonly underfilled to compensate for the mismatch in the Coefficient of Thermal Expansion (CTE) between the die and the chip carrier. The No Flow Underfill (NFU) process is a type that can increase the throughput of the flip chip assembly process and reduce manufacturing costs. Significant research has been performed to develop NFUs for eutectic applications. However, further research is required for the development of NFUs that are compatible with the Pb-free solders and the high temperature reflow process associated with these solders. In this paper, the challenges associated with the development of 'filled' underfill formulations for assembly with the 95.5Sn/3.8Ag/0.7Cu bumped flip chip devices are discussed. The effects of process variables that affect voiding in the underfill layer have been presented. The impact on voiding due to stencil printing of the underfill has been discussed. The impact on assembly reliability due to the underfill material properties has also been reported.

scholarly journals RSOB Shorting Defect Resolution through Looping Optimization and Ball Placement at Wirebond Process

2021 ◽  
pp. 34-38
Author(s):  
Norman S. Calma ◽  
Jonathan C. Pulido ◽  
Frederick Ray I. Gomez
Keyword(s):  
Parameter Optimization ◽  
Manufacturing Process ◽  
Packaging Industry ◽  
The Wire ◽  
Semiconductor Packaging

Wirebonding process is one of the most challenging assembly manufacturing process in semiconductor packaging industry. This paper discussed the wirebonding challenge and the solution to resolve the wire to die shorting on reverse stitch on ball (RSOB) and prevent irregular looping height for the substrate land grid array (LGA) device. Comprehensive parameter optimization was done particularly on the wirebond looping to ensure that no wire depression and no capillary hitting would occur wirebonding setup. Ultimately, the optimized wirebonding parameter prevented the occurrence of looping issues during the lot process.  For future works, the configuration and technique could be applied on packages with similar situation.

scholarly journals Assembly Wirebond Process Solution for Mitigating Leadframe Bouncing on Multi-Die QFN Device

2021 ◽  
pp. 7-12
Author(s):  
Raymond Albert A. Narvadez ◽  
Frederick Ray I. Gomez ◽  
Anthony R. Moreno ◽  
Edwin M. Graycochea Jr.
Keyword(s):  
Usual Practice ◽  
Package Design ◽  
Process Solution ◽  
Tooling Design ◽  
Packaging Industry ◽  
Assembly Problem ◽  
The Stability ◽  
Bouncing Effect ◽  
Multiple Holes ◽  
Semiconductor Packaging

Modification and improvement of an existing tooling design in semiconductor packaging industry has been a usual practice, to enhance the current setup and to provide a solution to a specific assembly problem. This paper discusses the solution in eliminating the smashed ball defect occurrence observed after wirebond process. Smashed ball is usually encountered if the unit is unstable and creates a bouncing effect during wirebond process. It is therefore important to mitigate this micro-bouncing effect by analyzing the package design and the window clamp and top plate (WCTP). The objective is to increase the stability of the unit during wirebonding, especially for quad-flat no-leads (QFN) package with no tape. To achieve this, the solution is to alter the vacuum hole design of the top plate from single hole per unit to multiple holes of varied sizes per unit. Ultimately, after changing the design of the top plate, the micro-bouncing encountered during wirebond process was significantly reduced. This in turn created a consistent ball formation in all bonded wires. The comparative data presented in this paper confirmed the effectivity of the redesigned WCTP. For future works and studies, the improvement and learnings could be used on devices with comparable configuration.

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