III-V / Si Heterojunction based Dual Material Stack Gate Oxide TFETs for Low Power Applications

2021 ◽  
Author(s):  
Dharmender ◽  
Kaushal Nigam ◽  
Satyendra Kumar
Keyword(s):  
Low Power ◽  
Gate Oxide ◽  
Dual Material

Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Speed ◽  
High Performance ◽  
Gate Oxide ◽  
Chemical Cleaning ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K ◽  
Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

scholarly journals Effect of Step Gate Work Function on InGaAs p-TFET for Low Power Switching Applications

Nanomaterials ◽  
2021 ◽  
Vol 11 (12) ◽  
pp. 3166
Author(s):  
Sayed Md Tariful Azam ◽  
Abu Saleh Md Bakibillah ◽  
Md Tanvir Hasan ◽  
Md Abdus Samad Kamal
Keyword(s):  
Low Power ◽  
Work Function ◽  
Potential Candidate ◽  
Gate Electrodes ◽  
The Future ◽  
Work Function Difference ◽  
High Transconductance ◽  
Dual Material ◽  
Gate Work Function ◽  
Function Difference

In this study, we theoretically investigated the effect of step gate work function on the InGaAs p-TFET device, which is formed by dual material gate (DMG). We analyzed the performance parameters of the device for low power digital and analog applications based on the gate work function difference (∆ϕS-D) of the source (ϕS) and drain (ϕD) side gate electrodes. In particular, the work function of the drain (ϕD) side gate electrodes was varied with respect to the high work function of the source side gate electrode (Pt, ϕS = 5.65 eV) to produce the step gate work function. It was found that the device performance varies with the variation of gate work function difference (∆ϕS-D) due to a change in the electric field distribution, which also changes the carrier (hole) distribution of the device. We achieved low subthreshold slope (SS) and off-state current (Ioff) of 30.89 mV/dec and 0.39 pA/µm, respectively, as well as low power dissipation, when the gate work function difference (∆ϕS-D = 1.02 eV) was high. Therefore, the device can be a potential candidate for the future low power digital applications. On the other hand, high transconductance (gm), high cut-off frequency (fT), and low output conductance (gd) of the device at low gate work function difference (∆ϕS-D = 0.61 eV) make it a viable candidate for the future low power analog applications.

2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO2/HfO2 Stacked Gate-Oxide Structure

2017 ◽  
Vol 64 (3) ◽  
pp. 960-968 ◽  
Author(s):  
Sanjay Kumar ◽  
Ekta Goel ◽  
Kunal Singh ◽  
Balraj Singh ◽  
Prince Kumar Singh ◽  
...  
Keyword(s):  
Analytical Modeling ◽  
Gate Oxide ◽  
Double Gate ◽  
Electrical Characteristics ◽  
Oxide Structure ◽  
Dual Material

Asymmetric Underlap Dual Material Gate DG-FET for Low Power Analog/RF Applications

2015 ◽  
Vol 11 (4) ◽  
pp. 509-516 ◽  
Author(s):  
Atanu Kundu ◽  
Arka Dutta ◽  
Chandan K. Sarkar
Keyword(s):  
Low Power ◽  
Rf Applications ◽  
Dual Material

scholarly journals A Novel Approach for Design and Investigation of Dual Material Stack Gate Oxide TFET using Oxide Strip Layer Mechanism

2021 ◽  
Author(s):  
Kaushal Nigam ◽  
Dharmender Nishad
Keyword(s):  
Computer Aided Design ◽  
Gate Oxide ◽  
Subthreshold Swing ◽  
Power Switching ◽  
Novel Approach ◽  
Drain Side ◽  
Work Functions ◽  
Oxide Tunnel ◽  
Aided Design ◽  
Dual Material

Abstract In this paper, for the first time, we use a distinctive approach based on oxide strip layer in dual material stack gate oxide-tunnel field-effect transistor (DMSGO-OSL-TFET) to improve the DC, analog/RF, and linearity performance. For this, a stack gate oxide with workfunction is considered to enhance the ONstate current (ION ) and reduce the ambipolar current (Iamb). For this case, the gate electrode is tri-segmented, named as tunnel gate (M1), control gate (M2) and auxiliary gate (M3) with different gate lengths (L1, L2, L3) and work functions (φ1, φ2, φ3), respectively. To maintain dual-work functionality, the possible combinations of these work functions are considered. Technology computer-aided design (TCAD) simulations are performed and noted that the workfunction combination (φ1 = φ3 < φ2) outperforms compared to other structures. Where φ1 on the source side is used to enhance the ION , while φ3 (equal to φ1) is used on the drain side to minimize the Iamb. To further enhance the device performance, a high-K oxide strip layer is considered on the drain side to suppress the (Iamb) whereas, a low-K oxide strip layer is used at the source junction to maximize the ION . Moreover, length of gate segments, oxide strip layer height, and thickness are optimized to achieve a better ION , switching ratio, subthreshold swing (SS) and reduce the (Iamb) which helps in the gain of device and design of analog/RF circuits. The proposed device as compared to dual material control gate-oxide strip layer-TFET (DMCG-OSL-TFET) shows improvement in ION /IOF F (∼ 4.23 times), 84 % increase in transconductance (gm), 136 % increase in cut-off frequency (fT ), 126 % increase in gain bandwidth product (GBP), point subthreshold swing (15.8 mV/decade) and other significant improvements in linearity performance parameters such as gm3, VIP3, IIP3, IMD3 making the proposed device useful for low power switching, analog/RF and linearity applications.

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