A compatible low-noise multi-phase voltage-controlled-oscillator

Author(s):  
Heng-zhou Yuan ◽  
Yang Guo ◽  
Jia-wei Tan ◽  
Qian-cheng Guo
Author(s):  
Shitesh Tiwari ◽  
Sumant Katiyal ◽  
Parag Parandkar

Voltage Controlled Oscillator (VCO) is an integral component of most of the receivers such as GSM, GPS etc. As name indicates, oscillation is controlled by varying the voltage at the capacitor of LC tank. By varying the voltage, VCO can generate variable frequency of oscillation. Different VCO Parameters are contrasted on the basis of phase noise, tuning range, power consumption and FOM. Out of these phase noise is dependent on quality factor, power consumption, oscillation frequency and current. So, design of LC VCO at low power, low phase noise can be obtained with low bias current at low voltage.  Nanosize transistors are also contributes towards low phase noise. This paper demonstrates the design of low phase noise LC VCO with 4.89 GHz tuning range from 7.33-11.22 GHz with center frequency at 7 GHz. The design uses 32nm technology with tuning voltage of 0-1.2 V. A very effective Phase noise of -114 dBc / Hz is obtained with FOM of -181 dBc/Hz. The proposed work has been compared with five peer LC VCO designs working at higher feature sizes and outcome of this performance comparison dictates that the proposed work working at better 32 nm technology outperformed amongst others in terms of achieving low Tuning voltage and moderate FoM, overshadowed by a little expense of power dissipation. 


2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.


Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6456
Author(s):  
Fernando Cardes ◽  
Nikhita Baladari ◽  
Jihyun Lee ◽  
Andreas Hierlemann

This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.


Sensors ◽  
2022 ◽  
Vol 22 (2) ◽  
pp. 504
Author(s):  
Ranran Zhao ◽  
Yuming Zhang ◽  
Hongliang Lv ◽  
Yue Wu

This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 μm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential structure charge pump (CP) are proposed respectively. In addition, a low noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider is realized. Finally, the phase locked loop (PLL) is realized by cascading each module. Measurement results show that the output signal frequency of the proposed CPPLL is 3.584 GHz–4.021 GHz, the phase noise at the frequency offset of 1 MHz is −117.82 dBc/Hz, and the maximum output power is 4.34 dBm. The chip area is 2701 μm × 3381 μm, and the power consumption is 181 mw.


Author(s):  
Tran Van Hoi ◽  
Ngo Thi Lanh ◽  
Nguyen Xuan Truong ◽  
Nguyen Huu Duc ◽  
Bach Gia Duong

<p>This paper focuses on the design and implementation of a front-end for a Vinasat satellite receiver with auto-searching mechanism and auto-tracking satellite. The front-end consists of a C-band low-noise block down-converter and a L-band receiver. The receiver is designed to meet the requirements about wide-band, high sensitivity, large dynamic range, low noise figure. To reduce noise figure and increase bandwidth, the C-band low-noise amplifier is designed using T-type of matching network with negative feedback and the L-band LNA is designed using cascoded techniques. The local oscillator uses a voltage controlled oscillator combine phase locked loop to reduce the phase noise and select channels. The front-end has successfully been designed and fabricated with parameters: Input frequency is C-band; sensitivity is greater than -130 dBm for C-band receiver and is greater than -110dBm for L-band receiver; output signals are AM/FM demodulation, I/Q demodulation, baseband signals.</p>


2014 ◽  
Vol 35 (9) ◽  
pp. 095007 ◽  
Author(s):  
Peng Qin ◽  
Jinbo Li ◽  
Jian Kang ◽  
Xiaoyong Li ◽  
Jianjun Zhou

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