Demonstration of Conductive Bridging Random Access Memory (CBRAM) in Logic CMOS Process

2010 ◽  
Author(s):  
Chakravarthy Gopalan ◽  
Yi Ma ◽  
Tony Gallo ◽  
Janet Wang ◽  
Ed Runnion ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Cmos Process ◽  
Access Memory

Design of Dynamic Random Access Memory Refresh Circuit Based on Temperature

2021 ◽  
Vol 16 (2) ◽  
pp. 235-242
Author(s):  
Wan-Jun Yin ◽  
Zheng-Feng Ming ◽  
Tao Wen ◽  
Yi-Xue Yuan
Keyword(s):  
High Temperature ◽  
Power Consumption ◽  
Random Access ◽  
Random Access Memory ◽  
Cmos Process ◽  
Access Memory ◽  
Storage Unit ◽  
The Core ◽  
Simulation Results ◽  
Core Storage

This paper proposed a temperature adaptive refresh circuit for traditional memory with fixed refresh frequency, high refresh power consumption at low temperature and low refresh frequency at high temperature. The 2T core storage unit combining with the existing CMOS process and circuit is taking as the research object, considering the characteristics of temperature rising, leakage current increasing, information holding time shortening, and the various constraints between the area, power consumption and other performance, this paper proposes to add the same redundant unit as the storage array to the storage array as the temperature monitoring circuit to realize the adaptive refresh function, and designs the core circuit. The simulation results show that the design of SMIC 0.09 um standard CMOS process fully meets the requirements of memory adaptive refresh.

Demonstration of Conductive Bridging Random Access Memory (CBRAM) in logic CMOS process

2011 ◽  
Vol 58 (1) ◽  
pp. 54-61 ◽  
Author(s):  
C. Gopalan ◽  
Y. Ma ◽  
T. Gallo ◽  
J. Wang ◽  
E. Runnion ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Cmos Process ◽  
Access Memory

Integrating MTJ Devices into a 130nm CMOS Process Flow

2016 ◽  
Vol 99 ◽  
pp. 81-89
Author(s):  
Miryam Buchbinder ◽  
Ora Eli ◽  
Sagie Rozental ◽  
Yami Bouhnik ◽  
Shimon Greenberg ◽  
...  
Keyword(s):  
Process Development ◽  
Random Access ◽  
Random Access Memory ◽  
Magnetic Sensors ◽  
Cmos Process ◽  
Main Process ◽  
Access Memory ◽  
Lower Electrode ◽  
Magnetic Random Access Memory ◽  
Cell Element

A Magnetic Random Access Memory (MRAM) device was successfully embedded into TowerJazz’s 130nm CMOS platform. The fabricated devices are stand-alone 4Mbit and 1Mbit MRAM memories and Multi-MLU magnetic sensors. This paper will describe the process development challenges in adapting a standard 130nm Cu BEOL to incorporate the magnetic cell element, and the device sensitivities to processing.The main process challenges to be discussed are 1) formation of shallow damascene Cu contacts to the lower electrode; 2) patterning of the 150nm magnetic cell both lithography and etching of the magnetic stack; 3) planarization of the topography from the magnetic cell; 4) formation of dual damascene VIA’s to both the magnetic cell upper electrode and to the CMOS. Some electrical yield results of the stand-alone MRAM memory and magnetic sensors will be presented. This project was a collaborative effort between TowerJazz and Crocus Technology

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

Deprocessing Methodologies for Detection of IBC and Cell-to-Cell Shorts in Submicron DRAM

2012 ◽  
Author(s):  
Ramachandra Chitakudige ◽  
Sarat Kumar Dash ◽  
A.M. Khan
Keyword(s):  
High Selectivity ◽  
Electron Cyclotron Resonance ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Plasma System ◽  
Poly Silicon ◽  
Hazardous Gases ◽  
Wet Etch ◽  
Resonance Plasma

Abstract Detection of both Insufficient Buried Contact (IBC) and cell-to-cell short defects is quite a challenging task for failure analysis in submicron Dynamic Random Access Memory (DRAM) devices. A combination of a well-controlled wet etch and high selectivity poly silicon etch is a key requirement in the deprocessing of DRAM for detection of these types of failures. High selectivity poly silicon etch methods have been reported using complicated system such as ECR (Electron Cyclotron Resonance) Plasma system. The fact that these systems use hazardous gases like Cl2, HBr, and SF6 motivates the search for safer alternative deprocessing chemistries. The present work describes high selectivity poly silicon etch using simple Reactive Ion Etch (RIE) plasma system using less hazardous gases such as CF4, O2 etc. A combination of controlled wet etch and high selectivity poly silicon etch have been used to detect both IBC and cell-to-cell shorts in submicron DRAMs.

Challenges and Benefits of Product-Like SRAM in Technology Development

2011 ◽  
Author(s):  
Felix Beaudoin ◽  
Stephen Lucarini ◽  
Fred Towler ◽  
Stephen Wu ◽  
Zhigang Song ◽  
...  
Keyword(s):  
Technology Development ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Development Phase ◽  
High Complexity ◽  
Access Memory ◽  
Integration Schemes ◽  
Front End

Abstract For SRAMs with high logic complexity, hard defects, design debug, and soft defects have to be tackled all at once early on in the technology development while innovative integration schemes in front-end of the line are being validated. This paper presents a case study of a high-complexity static random access memory (SRAM) used during a 32nm technology development phase. The case study addresses several novel and unrelated fail mechanisms on a product-like SRAM. Corrective actions were put in place for several process levels in the back-end of the line, the middle of the line, and the front-end of the line. These process changes were successfully verified by demonstrating a significant reduction of the Vmax and Vmin nest array block fallout, thus allowing the broader development team to continue improving random defectivity.

Effect of Conductive Filament Temperature on ZrO2 based Resistive Random Access Memory Devices

2020 ◽  
Vol 12 (2) ◽  
pp. 02008-1-02008-4
Author(s):  
Pramod J. Patil ◽  
◽  
Namita A. Ahir ◽  
Suhas Yadav ◽  
Chetan C. Revadekar ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Memory Devices ◽  
Access Memory ◽  
Conductive Filament ◽  
Filament Temperature

scholarly journals Improved Device Distribution in High-Performance SiNx Resistive Random Access Memory via Arsenic Ion Implantation

Nanomaterials ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 1401
Author(s):  
Te Jui Yen ◽  
Albert Chin ◽  
Vladimir Gritsenko
Keyword(s):  
High Performance ◽  
Conduction Mechanism ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Switching Behavior ◽  
Access Memory ◽  
Current Voltage ◽  
Current Voltage Characteristics ◽  
Limited Conduction

Large device variation is a fundamental challenge for resistive random access memory (RRAM) array circuit. Improved device-to-device distributions of set and reset voltages in a SiNx RRAM device is realized via arsenic ion (As+) implantation. Besides, the As+-implanted SiNx RRAM device exhibits much tighter cycle-to-cycle distribution than the nonimplanted device. The As+-implanted SiNx device further exhibits excellent performance, which shows high stability and a large 1.73 × 103 resistance window at 85 °C retention for 104 s, and a large 103 resistance window after 105 cycles of the pulsed endurance test. The current–voltage characteristics of high- and low-resistance states were both analyzed as space-charge-limited conduction mechanism. From the simulated defect distribution in the SiNx layer, a microscopic model was established, and the formation and rupture of defect-conductive paths were proposed for the resistance switching behavior. Therefore, the reason for such high device performance can be attributed to the sufficient defects created by As+ implantation that leads to low forming and operation power.

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