Continuous-time common-mode feedback for high-speed switched-capacitor networks

2005 ◽  
Vol 40 (8) ◽  
pp. 1610-1617 ◽  
Author(s):  
D. Hernandez-Garduno ◽  
J. Silva-Martinez
2014 ◽  
Vol 23 (05) ◽  
pp. 1450065 ◽  
Author(s):  
TOHID MORADI KHANESHAN ◽  
SAEED NAGHAVI ◽  
MOJDE NEMATZADE ◽  
KHAYROLLAH HADIDI ◽  
ADIB ABRISHAMIFAR ◽  
...  

A high-speed and high-accuracy continuous-time common-mode feedback block (CMFB) is presented. To satisfy speed and accuracy requirements, some modifications have been applied on differential difference amplifier (DDA) CMFB circuit. The proposed method is applied to a folded cascode op-amp with power supply of 3.3 V. In order to verify the proposed circuit, simulations are done in 0.35 μm standard CMOS technology. In the worst condition when the output common-mode (CM) voltage is initialized to VCC or GND, only 1.1 ns is required to set the output CM voltage on the desired level. Also in a wide range of input CM voltage variations, the deviation of the output CM voltage from reference voltage is less than 6 mV, so simulation results confirm the expected accuracy and speed while simultaneously the proposed CMFB circuit preserves other characteristics of DDA CMFB circuit such as unity gain frequency, 3-dB bandwidth, phase margin and linearity.


2008 ◽  
Vol 44 (21) ◽  
pp. 1225 ◽  
Author(s):  
F.A. Amoroso ◽  
A. Pugliese ◽  
G. Cappuccino ◽  
G. Cocorullo

2020 ◽  
Vol 29 (14) ◽  
pp. 2050223
Author(s):  
Joydeep Basu ◽  
Pradip Mandal

For stabilizing the common-mode output voltage of fully differential operational amplifiers, switched-capacitor (SC) type of common-mode feedback (CMFB) is a familiar technique. This is appropriate for implementing high-gain wide-swing low-power op-amps due to its benefits of minimum power consumption, superior linearity across a large amplifier output swing range, and improved feedback loop stability in comparison to continuous-time CMFB. However, the usage of SC-CMFB requires careful attention to some realistic aspects, details of many of which are available in literature. Nonetheless, its adverse effect on the op-amp’s differential-mode gain has not been investigated much. The explanation for this effect is the SC-CMFB-induced equivalent resistive loading, and this is particularly significant in amplifiers like folded cascode which are intended to provide a high gain. This issue of drop in op-amp dc gain because of SC-CMFB, and the consequence on the realization of continuous-time and discrete-time forms of integrators utilizing such amplifiers is the topic of discussion in this paper. Relevant analytical derivations and circuit simulations at the transistor level are provided. A couple of design guidelines and circuit topologies for minimizing the loading-induced gain reduction are also presented.


2005 ◽  
Vol 15 (02) ◽  
pp. 459-476
Author(s):  
C. PATRICK YUE ◽  
JAEJIN PARK ◽  
RUIFENG SUN ◽  
L. RICK CARLEY ◽  
FRANK O'MAHONY

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.


2010 ◽  
Vol 19 (03) ◽  
pp. 519-528 ◽  
Author(s):  
M. PRAMOD ◽  
T. LAXMINIDHI

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 μm CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27–34% less power than previous high swing CMFB circuits.


2014 ◽  
Vol 2014 ◽  
pp. 1-20
Author(s):  
Bodhisatwa Sadhu ◽  
Martin Sturm ◽  
Brian M. Sadler ◽  
Ramesh Harjani

This paper explores passive switched capacitor based RF receiver front ends for spectrum sensing. Wideband spectrum sensors remain the most challenging block in the software defined radio hardware design. The use of passive switched capacitors provides a very low power signal conditioning front end that enables parallel digitization and software control and cognitive capabilities in the digital domain. In this paper, existing architectures are reviewed followed by a discussion of high speed passive switched capacitor designs. A passive analog FFT front end design is presented as an example analog conditioning circuit. Design methodology, modeling, and optimization techniques are outlined. Measurements are presented demonstrating a 5 GHz broadband front end that consumes only 4 mW power.


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