A strategy for mixed-signal yield improvement

2002 ◽  
Vol 19 (3) ◽  
pp. 12-21 ◽  
Author(s):  
J. Bordelon ◽  
B. Tranchina ◽  
V. Madangarli ◽  
M. Craig
Author(s):  
Daeik Kim ◽  
Choongyeun Cho ◽  
Jonghae Kim ◽  
Jean-olivier Plouchart ◽  
Robert Trzcinski ◽  
...  

2013 ◽  
Vol 61 (3) ◽  
pp. 691-696 ◽  
Author(s):  
R. Suszynski ◽  
K. Wawryn

Abstract A rapid prototyping method for designing mixed signal systems has been presented in the paper. The method is based on implementation of the field programmable analog array (FPAA) to configure and reconfigure mixed signal systems. A serial algorithmic analog digital converter has been used as an example. Three converter architectures have been selected and implemented FPAA device. To verify and illustrate converters operation and prototyping capabilities, implemented converters have been excited by a sinusoidal signal. Analog sinusoidal excitations, digital responses and sinusoidal waveforms after reconstruction are presented.


2012 ◽  
Vol 1 (1) ◽  
pp. 1-7
Author(s):  
Vadim Geurkov ◽  
◽  
Lev Kirischian ◽  
Keyword(s):  

Author(s):  
Jenny Fan ◽  
Dave Mark

Abstract Metal interconnect defects have become a more serious yield detractor as backend process complexity has increased from a single layer to about 10 layers. This paper introduces a test methodology to monitor and localize the metal defects based on FPGA products. The test patterns are generated for each metal layer. The results not only indicate the severity of defects for each metal layer, but also accurately isolate open/short defects.


Author(s):  
Chunyu Zhang ◽  
Lakshmi Vedula ◽  
Shekhar Khandekar

Abstract Latch-up induced during High Temperature Operating Life (HTOL) test of a mixed signal device fabricated with 1.0 μm CMOS, double poly, double metal process caused failures due to an open in aluminum metal line. Metal lines revealed wedge voids of about 50% of the line width. Triggering of latch up mechanism during the HTOL test resulted in a several fold increase of current flowing through the ground metal line. This increase in current resulted in the growth of the wedge voids leading to failures due to open metal lines.


Author(s):  
Julie Segal ◽  
Arman Sagatelian ◽  
Bob Hodgkins ◽  
Tom Ho ◽  
Ben Chu ◽  
...  

Abstract Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.


Author(s):  
J. Douglass ◽  
T. D. Myers ◽  
F. Tsai ◽  
R. Ketcheson ◽  
J. Errett

Abstract This paper describes how the authors used a combination of focused ion beam (FIB) microprobing, transmission electron microscopy (TEM), and data and process analysis to determine that localized water residue was causing a 6% yield loss at die sort.


Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.


Crop Science ◽  
1992 ◽  
Vol 32 (3) ◽  
pp. 718-722 ◽  
Author(s):  
E. Martínez‐Barajas ◽  
C. Villanueva‐Verduzco ◽  
J. Molina‐Galán ◽  
H. Loza‐Tavera ◽  
E. Sánchez‐de‐Jiménez

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