New fully differential instrumental chain for Hall sensor signal conditioning integrated in standard 0.35 μm CMOS process

Author(s):  
Cyrius Ouffoue ◽  
Vincent Frick ◽  
Christian Kern ◽  
Luc Hebrard
Author(s):  
Jorge Pérez Bailón ◽  
Jaime Ramírez-Angulo ◽  
Belén Calvo ◽  
Nicolás Medrano

This paper presents a Variable Gain Amplifier (VGA) designed in a 0.18 μm CMOS process to operate in an impedance sensing interface. Based on a transconductance-transimpedance (TC-TI) approach with intermediate analog-controlled current steering, it exhibits a gain ranging from 5 dB to 38 dB with a constant bandwidth around 318 kHz, a power consumption of 15.5 μW at a 1.8 V supply and an active area of 0.021 mm2.


Sensors ◽  
2018 ◽  
Vol 18 (12) ◽  
pp. 4199 ◽  
Author(s):  
Behnam Samadpoor Rikan ◽  
Sang-Yun Kim ◽  
Nabeel Ahmad ◽  
Hamed Abbasizadeh ◽  
Muhammad Riaz Ur Rehman ◽  
...  

This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.


2019 ◽  
Vol 17 (06) ◽  
pp. 937-944
Author(s):  
Renata I. S. Pereira ◽  
Sandro C. S. Juca ◽  
Paulo C. M. Carvalho ◽  
Cleonilson P. Souza

2015 ◽  
Vol 24 (06) ◽  
pp. 1550078 ◽  
Author(s):  
Seid Jafar Hosseinipouya ◽  
Farhad Dastadast

High performance of fully differential operational transconductance amplifier is designed and implemented using a 0.18-μm CMOS process. The implemented op-amp uses common mode feedback (CMFB) circuit operating in weak inversion region which does not affect other electrical characteristics due to eliminating common mode (CM) levels automatically leading to improve CM rejection ratio (CMRR) of the amplifier significantly. Moreover, the output stage has class-AB operation so that its current can be made larger due to increasing the output current dynamically using adaptive biasing circuit. Additionally, the AC currents of the active loads have been significantly reduced using negative impedances to increase the gain of the amplifier. The results show the GBW 2.3 MHz, slew rate 2.6 V/μs and 1% settling time 150 ns with a capacitive load of 15 pF. This amplifier dissipates only 6.2 μW from a 1.2 V power supply.


2019 ◽  
Vol 10 (1) ◽  
pp. 63 ◽  
Author(s):  
Yongsu Kwon ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Kwonsang Han ◽  
Donggeun You ◽  
...  

A fully differential multipath current-feedback instrumentation amplifier (CFIA) for a resistive bridge sensor readout integrated circuit (IC) is proposed. To reduce the CFIA’s own offset and 1/f noise, a chopper stabilization technique is implemented. To attenuate the output ripple caused by chopper up-modulation, a ripple reduction loop (RRL) is employed. A multipath architecture is implemented to compensate for the notch in the chopping frequency band of the transfer function. To prevent performance degradation resulting from external offset, a 12-bit R-2R digital-to-analog converter (DAC) is employed. The proposed CFIA has an adjustable gain of 16–44 dB with 5-bit programmable resistors. The proposed resistive sensor readout IC is implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. The CFIA draws 169 μA currents from a 3.3 V supply. The simulated input-referred noise and noise efficiency factor (NEF) are 28.3 nV/√Hz and 14.2, respectively. The simulated common-mode rejection ratio (CMRR) is 162 dB, and the power supply rejection ratio (PSRR) is 112 dB.


2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001818-001850 ◽  
Author(s):  
Glenn G. Daves

The long-term trend in automobiles has been increasing electronics content over time. This trend is expected to continue and drives diverse functional, form factor, and reliability requirements. These requirements, in turn, are leading to changes in the package types selected and the performance specifications of the packages used for automotive electronics. Several examples will be given. This abstract covers the development of a distributed high temperature electronics demonstrator for integration with sensor elements to provide digital outputs that can be used by the FADEC (Full Authority Digital Electronic Control) system or the EHMS (Engine Health Monitoring System) on an aircraft engine. This distributed electronics demonstrator eliminates the need for the FADEC or EHMS to process the sensor signal, which will assist in making the overall system more accurate and efficient in processing only digital signals. This will offer weight savings in cables, harnesses and connector pin reduction. The design concept was to take the output from several on-engine sensors, carry out the signal conditioning, multiplexing, analogue to digital conversion and data transmission through a serial data bus. The unit has to meet the environmental requirements of DO-160 with the need to operate at 200°C, with short term operation at temperatures up to 250°C. The work undertaken has been to design an ASIC based on 1.0 μm Silicon on Insulator (SOI) device technology incorporating sensor signal conditioning electronics for sensors including resistance temperature probes, strain gauges, thermocouples, torque and frequency inputs. The ASIC contains analogue multiplexers, temperature stable voltage band-gap reference and bias circuits, ADC, BIST, core logic, DIN inputs and two parallel ARINC 429 serial databuses. The ASIC was tested and showed to be functional up to a maximum temperature of 275°C. The ASIC has been integrated with other high temperature components including voltage regulators, a crystal oscillator, precision resistors, silicon capacitors within a hermetic hybrid package. The hybrid circuit has been assembled within a stainless steel enclosure with high temperature connectors. The high temperature electronics demonstrator has been demonstrated operating from −40°C to +250°C. This work has been carried out under the EU Clean Sky HIGHTECS project with the Project being led by Turbomeca (Fr) and carried out by GE Aviation Systems (UK), GE Research – Munich (D) and Oxford University (UK).


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