Design and Verification of a 6.25 GHz LC-Tank VCO integrated in 65 nm CMOS Technology Operating up to 1 Grad TID

This work presented a comparison between two Voltage Controlled Oscillators (VCOs) designed in 65 nm CMOS technology. The first architecture based on a Ring Oscillator (RO) was designed using three Current Mode Logic (CML) stages connected in a loop, while the second one was based on an LC-tank resonator. This analysis aimed to choose a VCO architecture able to be integrated into a rad-hard Phase Locked Loop. It had to meet the requirements of the SpaceFibre protocol, which supports frequencies up to 6.25 GHz, for space applications. The full custom schematic and layout designs are shown, and Single Event Effect simulations results, performed with a double exponential current pulses generator, are presented in detail for both VCOs. Although the RO-VCO performances in terms of technology scaling and high-integration density were attractive, the simulations on the process variations demonstrated its inability to generate the target frequency in harsh operating conditions. Instead, the LC-VCO highlighted a lower influence through Process-Voltage-Temperature simulations on the oscillation frequency. Both architectures were biased with a supply voltage of 1.2 V. The achieved results for the second architecture analyzed were attractive to address the requirements of the new SpaceFibre aerospace standard.

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Design and simulation of pulse generator for UWB based on LC-tank differential oscillators topology

Science and Technology Development Journal ◽

10.32508/stdj.v18i3.840 ◽

2015 ◽

Vol 18 (3) ◽

pp. 225-241

Author(s):

Nhan Chi Nguyen ◽

Nghia Hoai Duong ◽

Anh Van Dinh

Keyword(s):

Pulse Generator ◽

Current Source ◽

Average Power ◽

Cmos Technology ◽

Negative Resistance ◽

Ultra Wideband ◽

Positive Gain ◽

Average Power Consumption ◽

Analysis Design ◽

Lc Tank

This paper presents a detailed analysis, design and simulation of pulse generator for Ultra-Wideband (UWB) based on LC-tank differential oscillators topology. The differential oscillators with a cross-coupled NMOS pair and a tail current source are used to achieve more positive gain and generate negative resistance to the LC-tank. Besides, this oscillator is suitable for UWB high frequency and low power applications. The UWB pulse generator is composed of a simple on-off keying (OOK) modulated and LC-tank differential oscillators. The circuit of UWB pulse generator designed and simulated in 0.13 um CMOS technology. The UWB pulse generator generates a pulse for the 6 - 10 GHz UWB transmitter. Simulation results show a pulse width of 586 ps, a peak to peak amplitude pulse of 88.6 mV from the 1.2 V power supply and the die area of 0.22 mm2. The average power consumption of approximately 0.55 mW and an energy consumption of 1.1 pJ/pulse at 500 MHz pulse repetition rate (PRR) are observed.

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LC Tank Differential Inductor-Coupled Dual-Core 60 GHz Push-Push VCO in 45 nm RF-SOI CMOS Technology

2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) ◽

10.1109/sirf.2019.8709120 ◽

2019 ◽

Cited By ~ 1

Author(s):

J. Rimmelspacher ◽

R. Weigel ◽

A. Hagelauer ◽

V. Issakov

Keyword(s):

Cmos Technology ◽

60 Ghz ◽

Lc Tank ◽

Dual Core ◽

Differential Inductor ◽

Soi Cmos

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Modellierungskonzept für MOS Varaktoren zur Minimierung der AM-FM Konversion in VCOs

Advances in Radio Science ◽

10.5194/ars-8-143-2010 ◽

2010 ◽

Vol 8 ◽

pp. 143-149

Author(s):

T. Peikert ◽

J.-K. Bremer ◽

W. Mathis

Keyword(s):

Simulation Model ◽

Cmos Technology ◽

Design Flow ◽

Design Parameters ◽

Cmos Process ◽

Large Signal ◽

Analytical Simulation ◽

Good Accordance ◽

Transistor Model ◽

Lc Tank

Abstract. In dieser Arbeit wird ein analytisches Simulationsmodell für MOS Varaktoren zur Entwurfsunterstützung von integrierten CMOS LC-Tank VCO-Schaltungen präsentiert. Das analytische Simulationsmodell wurde auf Basis des EKV-Transistormodells implementiert und beinhaltet ausschließlich Design- und Prozessparameter für die Berechnung der Varaktorkapazität. Dieses Simulationsmodell ermöglicht es, die verwendeten Varaktoren im Vorfeld des VCO-Entwurfs zu dimensionieren, die effektive Großsignalkapazität in Abhängigkeit des Ausgangssignals zu berechnen und einzelne Eigenschaften der Varaktoren, wie z.B. das AM-FM Konversionsverhalten zu optimieren. Die Gültigkeit des vorgestellten analytischen Simulationsmodells zur Beschreibung der Varaktorkapazität in CMOS LC-Tank VCOs, wird anhand von Spectre (Cadence) Simulationen auf Basis eines 0.25 μm CMOS Prozesses der Firma IHP (SGB25) und eines 0.35 μm CMOS Prozesses der Firma AMS (C35) verifiziert. In this work an analytical simulation model for MOS varactors, that can be used in a systematically VCO design flow, is presented. The simulation model is based on the EKV transistor model and includes only design and process parameters of the used CMOS technology. The proposed simulation model allows calculating the required design parameters and the effective large signal capacitance of the varactors incorporated into the VCO as a function of the output signal of the VCO. Based on the expression for the effective large signal capacitance it is possible to optimize the AM-FM conversion behavior of the used varactors. The validity and accuracy of the simulation model is verified by Spectre simulations which are based on a 0.25 μm CMOS process (SGB25) from the company IHP and a 0.35 μm CMOS process (C35) from the company AMS. The simulation results show a good accordance in all transistor operating regions for NMOS varactors as well as PMOS varactors.

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A 0.5~0.7 V LC Digitally Controlled Oscillator Based on a Multi-Stage Capacitance Shrinking Technique

Electronics ◽

10.3390/electronics8111336 ◽

2019 ◽

Vol 8 (11) ◽

pp. 1336

Author(s):

Zixuan Wang ◽

Hongyang Wu ◽

Xin Wang ◽

Mingmin Shi ◽

Shanwen Hu ◽

...

Keyword(s):

High Resolution ◽

Low Power ◽

Low Voltage ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Multi Stage ◽

Digitally Controlled ◽

Digitally Controlled Oscillator ◽

The Cost ◽

Lc Tank

This paper presents a 2.4 GHz LC digitally controlled oscillator (DCO) at near-threshold supplies (0.5~0.7 V). It was a challenge to achieve a low voltage, low power, and high resolution simultaneously. DCOs with metal oxide semiconductor (MOS) varactors consume low power, but their resolution is limited. ΔΣ-DCOs can achieve a high resolution at the cost of high power consumption. A multi-stage capacitance shrinking technique was proposed in this paper to address the tradeoff mentioned above. The unit variable capacitance of the LC tank was largely reduced by the bridging capacitors and the number of stages. A current-reuse technique was used to further lower the power. Based on the above techniques, the prototype was fabricated using a 130-nm complementary MOS (CMOS) technology with multiple supplies (0.5~0.7 V for the DCO core, 1.2 V for the buffer). The measurement results showed that the phase noise at a 0.6-V supply was −126.27 dBc/Hz at 1 MHz and −125.9480 dBc/Hz at 1 MHz at the carriers of 2.4 GHz and 2.5 GHz, respectively. The best figure of merit (FoM) of 195.68 was obtained when VDD = 0.6 V. The DCO core consumed 1.1 mA at a 0.6-V supply.

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