scholarly journals Modellierungskonzept für MOS Varaktoren zur Minimierung der AM-FM Konversion in VCOs

2010 ◽  
Vol 8 ◽  
pp. 143-149
Author(s):  
T. Peikert ◽  
J.-K. Bremer ◽  
W. Mathis
Keyword(s):  
Simulation Model ◽  
Cmos Technology ◽  
Design Flow ◽  
Design Parameters ◽  
Cmos Process ◽  
Large Signal ◽  
Analytical Simulation ◽  
Good Accordance ◽  
Transistor Model ◽  
Lc Tank

Abstract. In dieser Arbeit wird ein analytisches Simulationsmodell für MOS Varaktoren zur Entwurfsunterstützung von integrierten CMOS LC-Tank VCO-Schaltungen präsentiert. Das analytische Simulationsmodell wurde auf Basis des EKV-Transistormodells implementiert und beinhaltet ausschließlich Design- und Prozessparameter für die Berechnung der Varaktorkapazität. Dieses Simulationsmodell ermöglicht es, die verwendeten Varaktoren im Vorfeld des VCO-Entwurfs zu dimensionieren, die effektive Großsignalkapazität in Abhängigkeit des Ausgangssignals zu berechnen und einzelne Eigenschaften der Varaktoren, wie z.B. das AM-FM Konversionsverhalten zu optimieren. Die Gültigkeit des vorgestellten analytischen Simulationsmodells zur Beschreibung der Varaktorkapazität in CMOS LC-Tank VCOs, wird anhand von Spectre (Cadence) Simulationen auf Basis eines 0.25 μm CMOS Prozesses der Firma IHP (SGB25) und eines 0.35 μm CMOS Prozesses der Firma AMS (C35) verifiziert. In this work an analytical simulation model for MOS varactors, that can be used in a systematically VCO design flow, is presented. The simulation model is based on the EKV transistor model and includes only design and process parameters of the used CMOS technology. The proposed simulation model allows calculating the required design parameters and the effective large signal capacitance of the varactors incorporated into the VCO as a function of the output signal of the VCO. Based on the expression for the effective large signal capacitance it is possible to optimize the AM-FM conversion behavior of the used varactors. The validity and accuracy of the simulation model is verified by Spectre simulations which are based on a 0.25 μm CMOS process (SGB25) from the company IHP and a 0.35 μm CMOS process (C35) from the company AMS. The simulation results show a good accordance in all transistor operating regions for NMOS varactors as well as PMOS varactors.

Design and Fabrication of a Temperature Sensor Based on Thermopile in CMOS Technology

2003 ◽  
Author(s):  
Ioana Voiculescu ◽  
Mona Zaghloul ◽  
R. Andrew McGill
Keyword(s):  
Temperature Sensor ◽  
Silicon Oxide ◽  
Mechanical Stability ◽  
Cmos Technology ◽  
Nitride Layer ◽  
Design Parameters ◽  
Cmos Process ◽  
Post Processing ◽  
Test Chip ◽  
Optimal Geometry

This paper describes a new geometry for integrated micromachined thermopile structures. Different arrangements for the thermocouples in proximity to the heating element are examined, to optimize the accuracy of the temperature measurement. Several design parameters including thermopile lengths, and the number of thermocouples, are examined. The test chip was designed and fabricated in CMOS technology, including the appropriate opening for post-processing micromachining. The thermopile used was fabricated with polysilicon/aluminum contacts on a silicon oxide/nitride layer provided by the CMOS process. Different microbeam and bridge membrane support structures were designed for the thermopile, in order to investigate the optimal geometry for mechanical stability and to avoid structure buckling.

Evaluation of GALS Methods in Scaled CMOS Technology

2012 ◽  
Vol 3 (4) ◽  
pp. 1-18 ◽  
Author(s):  
Miloš Krstic ◽  
Xin Fan ◽  
Eckhard Grass ◽  
Luca Benini ◽  
M. R. Kakoee ◽  
...  
Keyword(s):  
Complex System ◽  
Cmos Technology ◽  
Network On Chip ◽  
Design Flow ◽  
Cmos Process ◽  
Test Results ◽  
Experimental Setting ◽  
Analysis Measurement ◽  
On Chip ◽  
Point To Point

In this paper the authors present the concept and evaluation results of a complex GALS ASIC demonstrator in 40 nm CMOS process. This chip, named Moonrake, compares synchronous and GALS synchronization technology in a homogeneous experimental setting: same baseline designs, same manufacturing process, same die. The chip validates GALS technology for both point-to-point and network-centric on-chip communications, demonstrating its potentials for different applications. The design analysis, measurement and test results confirm the potential of GALS approach for the scaled technologies, showing the significant benefits in respect to area, power, and EMI when it comes to the complex system implementation. Furthermore, 91% of the tests performed on the GALS network-on-chip test structures completed successfully, validating the timing robustness of new area and latency-efficient synchronization schemes and proving that the design flow for GALS synchronization technology can be implemented by means of mainstream industrial tools.

Silicon Validation of GALS Methods and Architectures in a State-of-the-Art CMOS Process

2014 ◽  
pp. 420-447
Author(s):  
Milos Krstic ◽  
Xin Fan ◽  
Eckhard Grass ◽  
Luca Benini ◽  
M. R. Kakoee ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Design Flow ◽  
Cmos Process ◽  
Special Test ◽  
Interface Circuits ◽  
Future Role ◽  
Measurement Results ◽  
Full Structure ◽  
Point To Point

The GALS methodology has been discussed for many years, but only a few relevant implementations in silicon have been done. This chapter describes the implementation and test of the Moonrake Chip – a complex GALS demonstrator implemented in 40 nm CMOS technology. Two novel types of GALS interface circuits are validated: point-to-point pausible clocking GALS interfaces and GALS NoC interconnects. Point-to-point GALS interfaces are integrated within a complex OFDM baseband transmitter block, and for NoC switches special test structures are defined. This chapter discloses the full structure of the respective interfaces, the complete GALS system, as well as the design flow utilized to implement them on the chip. Moreover, the full set of measurement results are presented, including area, power, and EMI results. Significant benefits and robustness of our applied GALS methodology are shown. Finally, some outlook and vision of the future role of GALS are outlined.

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Design and Layout of a High-Performance PWM Control Class D Amplifiers IC Systems

2012 ◽  
Vol 203 ◽  
pp. 469-473
Author(s):  
Ruei Chang Chen ◽  
Shih Fong Lee
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Voltage ◽  
Design Flow ◽  
Total Power ◽  
Cmos Process ◽  
Low Power Circuits ◽  
Class D ◽  
Total Power Consumption ◽  
Power Circuits

This paper presents the design and implementation of a novel pulse width modulation control class D amplifiers chip. With high-performance, low-voltage, low-power and small area, these circuits are employed in portable electronic systems, such as the low-power circuits, wireless communication and high-frequency circuit systems. This class D chip followed the chip implementation center advanced design flow, and then was fabricated using Taiwan Semiconductor Manufacture Company 0.35-μm 2P4M mixed-signal CMOS process. The chip supply voltage is 3.3 V which can operate at a maximum frequency of 100 MHz. The total power consumption is 2.8307 mW, and the chip area size is 1.1497×1.1497 mm2. Finally, the class D chip was tested and the experimental results are discussed. From the excellent performance of the chip verified that it can be applied to audio amplifiers, low-power circuits, etc.

A Practical Approach to Expedite a Pore to Process Simulation Model for a Rich Gas Condensate Reservoir – Case Study

2021 ◽  
Author(s):  
Mohamed Ibrahim Mohamed ◽  
Ahmed Mahmoud El-Menoufi ◽  
Eman Abed Ezz El-Regal ◽  
Ahmed Mohamed Ali ◽  
Khaled Mohamed Mansour ◽  
...  
Keyword(s):  
Simulation Model ◽  
Production Optimization ◽  
Operating Conditions ◽  
Gas Condensate ◽  
Western Desert ◽  
Design Parameters ◽  
Compositional Approach ◽  
Process Plant ◽  
Black Oil

Abstract Field development planning of gas condensate fields using numerical simulation has many aspects to consider that may lead to a significant impact on production optimization. An important aspect is to account for the effects of network constraints and process plant operating conditions through an integrated asset model. This model should honor proper representation of the fluid within the reservoir, through the wells and up to the network and facility. Obaiyed is one of the biggest onshore gas field in Egypt, it is a highly heterogeneous gas condensate field located in the western desert of Egypt with more than 100 wells. Three initial condensate gas ratios are existing based on early PVT samples and production testing. The initial CGRs as follows;160, 115 and 42 STB/MMSCF. With continuous pressure depletion, the produced hydrocarbon composition stream changes, causing a deviation between the design parameters and the operating parameters of the equipment within the process plant, resulting in a decrease in the recovery of liquid condensate. Therefore, the facility engineers demand a dynamic update of a detailed composition stream to optimize the system and achieve greater economic value. The best way to obtain this compositional stream is by using a fully compositional integrated asset model. Utilizing a fully compositional model in Obaiyed is challenging, computationally expensive, and impractical, especially during the history match of the reservoir numerical model. In this paper, a case study for Obaiyed field is presented in which we used an alternative integrated asset modeling approach comprising a modified black-oil (MBO) that results in significant timesaving in the full-field reservoir simulation model. We then used a proper de-lumping scheme to convert the modified black oil tables into as many components as required by the surface network and process plant facility. The results of proposed approach are compared with a fully compositional approach for validity check. The results clearly identified the system bottlenecks. The model can be used to propose the best tie-in location of future wells in addition to providing first-pass flow assurance indications throughout the field's life and under different network configurations. The model enabled the facility engineers to keep the conditions of the surface facility within the optimized operating envelope throughout the field's lifetime.

Numerical Efforts of Aerodynamic Re-Design in a Single-Stage Transonic Axial Compressor: Part 1 — Stator Design

2017 ◽  
Author(s):  
Justin (Jongsik) Oh
Keyword(s):  
Pressure Ratio ◽  
Axial Compressor ◽  
Axial Flow ◽  
Single Stage ◽  
Design Flow ◽  
Design Parameters ◽  
Original Design ◽  
Circular Arc ◽  
Surge Margin ◽  
Flow Compressor

In many aerodynamic design parameters for the axial-flow compressor, three variables of tailored blading, blade lean and sweep were considered in the re-design efforts of a transonic single stage which had been designed in 1960’s NASA public domains. As Part 1, the re-design was limited to the stator vane only. For the original MCA (Multiple Circular Arc) blading, which had been applied at all radii, the CDA (Controlled Diffusion Airfoil) blading was introduced at midspan as the first variant, and the endwalls of hub and casing (or tip) were replaced with the DCA (Double Circular Arc) blading for the second variant. Aerodynamic performance was predicted through a series of CFD analysis at design speed, and the best aerodynamic improvement, in terms of pressure ratio/efficiency and operability, was found in the first variant of tailored blading. It was selected as a baseline for the next design efforts with blade lean, sweep and both combined. Among 12 variants, a case of positively and mildly leaned blades was found the most attractive one, relative to the original design, providing benefits of an 1.0% increase of pressure ratio at design flow, an 1.7% increase of efficiency at design flow, a 10.5% increase of the surge margin and a 32.3% increase of the choke margin.

Sign in / Sign up

Export Citation Format

Share Document