Transition From MEMS Technology to Nanofabrication

2007 ◽  
Author(s):  
T. Glinsner ◽  
P. Lindner ◽  
P. Kettner ◽  
H. Kirchberger
Keyword(s):  
Nanoimprint Lithography ◽  
Low Cost ◽  
High Volume ◽  
Laboratory Research ◽  
High Yield ◽  
Mems Devices ◽  
Wafer Level ◽  
Industrial Processing ◽  
The Past ◽  
Mems Technology

The successful commercialization of Micro-Electro-Mechanical Systems (MEMS) from R&D to off-the-shelf products and systems has evolved from laboratory research to reliable and low cost industrial processing methods over the past 20 years. Standardization, infrastructure, roadmaps and industrial associations have been deemed key contributors for a successful transition and adaptation of microelectronics fabrication techniques to a specific nature of manufacturing MEMS devices resulted in turn key solutions for low cost, high yield and high volume wafer level processing. The need for smaller feature sizes as well as low cost manufacturing solutions has lead to significant improvements of the classical optical lithography in the past two decades following Moore’s law. Alternative patterning techniques are under development worldwide for producing patterns in the nm-range. There are similarities between MEMS and Nanofabrication requirement that allow for transitioning standardized and reliable processing technology from wafer bonding to hot embossing and from wafer level packaging to μ-CP and UV-based Nanoimprint Lithography.

scholarly journals Micro-electro-mechanical systems (MEMS): Technology for the 21st century

2014 ◽  
Vol 68 (5) ◽  
pp. 629-641 ◽  
Author(s):  
Tatjana Djakov ◽  
Ivanka Popovic ◽  
Ljubinka Rajakovic
Keyword(s):  
21St Century ◽  
Low Cost ◽  
Mechanical Systems ◽  
Modern Society ◽  
Global Scale ◽  
Thermal Constant ◽  
Mems Devices ◽  
Micro Electro Mechanical Systems ◽  
Industrial Sectors ◽  
Mems Technology

Micro-electro-mechanical systems (MEMS) are miniturized devices that can sense the environment, process and analyze information, and respond with a variety of mechanical and electrical actuators. MEMS consists of mechanical elements, sensors, actuators, electrical and electronics devices on a common silicon substrate. Micro-electro-mechanical systems are becoming a vital technology for modern society. Some of the advantages of MEMS devices are: very small size, very low power consumption, low cost, easy to integrate into systems or modify, small thermal constant, high resistance to vibration, shock and radiation, batch fabricated in large arrays, improved thermal expansion tolerance. MEMS technology is increasingly penetrating into our lives and improving quality of life, similar to what we experienced in the microelectronics revolution. Commercial opportunities for MEMS are rapidly growing in broad application areas, including biomedical, telecommunication, security, entertainment, aerospace, and more in both the consumer and industrial sectors on a global scale. As a breakthrough technology, MEMS is building synergy between previously unrelated fields such as biology and microelectronics. Many new MEMS and nanotechnology applications will emerge, expanding beyond that which is currently identified or known. MEMS are definitely technology for 21st century.

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000425-000445
Author(s):  
Paul Siblerud ◽  
Rozalia Beica ◽  
Bioh Kim ◽  
Erik Young
Keyword(s):  
Low Cost ◽  
Cost Effective ◽  
High Yield ◽  
Integrated Process ◽  
Wafer Level ◽  
Through Silicon Via ◽  
Wafer Level Packaging ◽  
Current State ◽  
Future Technologies ◽  
Ic Technology

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

Packaging Materials for 2.5/3D Technology

2013 ◽  
Vol 2013 (1) ◽  
pp. 000276-000284 ◽  
Author(s):  
Brian Schmaltz
Keyword(s):  
High Reliability ◽  
Low Cost ◽  
High Yield ◽  
Wafer Level ◽  
Reflow Process ◽  
Thermal Compression ◽  
Conductive Films ◽  
Cu Pillar ◽  
Advanced Packaging ◽  
Capillary Underfill

The age of advanced mobile devices is on the direct horizon, are we ready for it? Less power consumption, faster processing, high reliability, high yield, low cost are words engineers are all too familiar with. 2.5/3D utilizing interposer technology, Thru Silicon Via (TSV), sub-50μm die thickness are a few of the latest techniques engineers use to solve these issues. As technology progresses to smaller process generations, new packaging applications are being demanded. The standard solder reflow process is being pushed by advancements in Cu pillar bumps, thermal compression bonding (TCB) and wafer level / pre-applied materials. This presentation will centralize around the latest advancements in NAMICS Materials for Advanced Packaging Technology; Capillary Underfill (CUF), Pre-Applied Material, Non-Conductive Paste (NCP), Non-Conductive Films (NCF).

scholarly journals Design and Fabrication of Wafer-Level Microlens Array with Moth-Eye Antireflective Nanostructures

Nanomaterials ◽  
2019 ◽  
Vol 9 (5) ◽  
pp. 747 ◽  
Author(s):  
Shuping Xie ◽  
Xinjun Wan ◽  
Bo Yang ◽  
Wei Zhang ◽  
Xiaoxiao Wei ◽  
...  
Keyword(s):  
Nanoimprint Lithography ◽  
Production Efficiency ◽  
Low Cost ◽  
Microlens Array ◽  
Wafer Level ◽  
Lens Array ◽  
Wafer Level Packaging ◽  
High Production ◽  
Aspherical Lenses ◽  
Profile Accuracy

Wafer-level packaging (WLP) based camera module production has attracted widespread industrial interest because it offers high production efficiency and compact modules. However, suppressing the surface Fresnel reflection losses is challenging for wafer-level microlens arrays. Traditional dielectric antireflection (AR) coatings can cause wafer warpage and coating fractures during wafer lens coating and reflow. In this paper, we present the fabrication of a multiscale functional structure-based wafer-level lens array incorporating moth-eye nanostructures for AR effects, hundred-micrometer-level aspherical lenses for camera imaging, and a wafer-level substrate for wafer assembly. The proposed fabrication process includes manufacturing a wafer lens array metal mold using ultraprecise machining, chemically generating a nanopore array layer, and replicating the multiscale wafer lens array using ultraviolet nanoimprint lithography. A 50-mm-diameter wafer lens array is fabricated containing 437 accurate aspherical microlenses with diameters of 1.0 mm; each lens surface possesses nanostructures with an average period of ~120 nm. The microlens quality is sufficient for imaging in terms of profile accuracy and roughness. Compared to lenses without AR nanostructures, the transmittance of the fabricated multiscale lens is increased by ~3% under wavelengths of 400–750 nm. This research provides a foundation for the high-throughput and low-cost industrial application of wafer-level arrays with AR nanostructures.

MEMS Based Metal Plated Silicon Package for High Power LED

2006 ◽  
Vol 326-328 ◽  
pp. 309-312 ◽  
Author(s):  
Sung Jun Lee ◽  
Ji Hyun Park ◽  
Chang Hyun Lim ◽  
Won Kyu Jeong ◽  
Seog Moon Choi ◽  
...  
Keyword(s):  
Thermal Resistance ◽  
High Power ◽  
Power Dissipation ◽  
Heat Dissipation ◽  
High Efficiency ◽  
Low Cost ◽  
Wafer Level ◽  
High Power Led ◽  
Key Factor ◽  
Mems Technology

By the development of high power LED for solid states lighting, the requirement for driving current has increased critically, thereby increasing power dissipation. Heat flux corresponds to power dissipation is mainly generated in p-n junction of LED, so the effective removal of heat is the key factor for long lifetime of LED chip. In this study, we newly proposed the silicon package for high power LED using MEMS technology and estimated its heat dissipation characteristic. Our silicon package structure is composed of base and reflector cup. The role of base is that settle LED chip at desired position and supply electrical interconnection for LED operation, and finally transfer the heat from junction region to outside. For improved heat transfer, we introduced the heat conductive metal plated trench structure at the opposite side of LED attached side. The depth and the diameter of trench were 150 and 100um, respectively. Copper with high thermal conductivity than silicon was filled in trench by electroplating and the thickness of copper was about 100um. Reflector cup was formed by anisotropic wet etching and then, silicon package platform could be fabricated by eutectic bonding between base and reflector cup. The thermal resistance of silicon package was about 6 to 7K/W from junction to case, and also, thermal resistance reduction of 0.64K/W was done by metal plated trench. This result could be comparable to that of other high power LED package. Our silicon package platform is easy to be expanded into array and wafer level package. So, it is suitable for future high efficiency and low cost package.

Wafer-Level MEMS Package by Gold-Tin Bonding Method

2003 ◽  
Author(s):  
Sihai Chen ◽  
Sheng Liu ◽  
Mingxiang Chen ◽  
Tao Xiong ◽  
Daming Zhang ◽  
...  
Keyword(s):  
High Reliability ◽  
Low Cost ◽  
Local Heating ◽  
Mems Devices ◽  
Wafer Level ◽  
Eutectic Bonding ◽  
Heating Method ◽  
To Come ◽  
Bonding Method ◽  
Global Heating

This paper reports some results for an on-going program in wafer-level MEMS package Institute of Microsystems at Huazhong University of Science and Technology. The final goal was to come up with a method usable for various types of MEMS devices in wafer level so that the low cost and high reliability can be achieved at the same time. In this particular paper, three closed-loop microheaters of 5μm, 7μm and 9μm width were designed. By reactive ion sputtering technique, two classes of samples are presented. The first one was first co-sputtered with Ni/Cr and then sputtered with Au metal as heating with Ni/Cr and then sputtered with Au metal as heating material, the second one was sputtered with Cr, Sn and Au respectively as heating material. The bonding of the former sample based on the Ni/Cr and Au heating material failed. The eutectic bonding experiment of the later sample based on the Cr, Sn and Au heating material by global heating method was completed in annealing oven at temperature of about 400°C for 20 minutes and by local heating method was applyed current of 0.8 A into the microheater. The SEM testing result showed the eutectic bonding of Au-Sn by global heating was successful. More results will be reported during the conference presentation.

Low Cost Metal Mini-Cap Process for Suspended MEMS Device Packaging

2005 ◽  
Author(s):  
Wei Chung ◽  
Leonardo Wang ◽  
W. Fang
Keyword(s):  
Low Cost ◽  
Selective Etching ◽  
Mems Devices ◽  
Wafer Level ◽  
Carrier Wafer ◽  
Mems Device ◽  
Die Bonding ◽  
To Come ◽  
Wafer Level Package

A new wafer capping process is investigated in this study. The objective of this study is to come out a simple and low cost wafer capping process to make the capped MEMS device wafers “transparent” to traditional IC assembly processes. The carrier wafers with metal mini-caps are bonded on the MEMS device wafers through solder bonding, and the mini-caps are then transferred and left on the MEMS device wafer through a selective etching of the carrier wafers. The metal mini-cap capped device wafers are virtually of the same thickness as original ones; in addition, the transferred metal mini-caps provide a mechanical protection to the MEMS devices during the consequent assembly processes such as wafer dicing, die bonding, molding, etc. With an additional design of 2nd level interconnection on the mini-cap carrier wafer, the transferred MEMS device wafers can be singulated and become a wafer level package with compliant leads.

Microfabrication and Packaging Process for a Single-Chip Position, Navigation, and Timing System

2017 ◽  
Vol 2017 (1) ◽  
pp. 000208-000214 ◽  
Author(s):  
Junjun Huan ◽  
Vamsy P. Chodavarapu ◽  
George Xereas ◽  
Charles Allan
Keyword(s):  
Inertial Sensors ◽  
Low Cost ◽  
Autonomous Systems ◽  
Pressure Sensors ◽  
Single Crystal Silicon ◽  
High Volume ◽  
Leak Rate ◽  
Single Chip ◽  
Wafer Level ◽  
Crystal Silicon

Abstract The Global Positioning System (GPS) is the primary means of Positioning, Navigation, and Timing (PNT) for most civilian and military systems and applications. The rapid growth in autonomous systems has created a widespread interest in self-contained Inertial Navigation System (INS) for precise navigation and guidance in the absence of GPS. The microscale PNT systems need both specialized and low cost fabrication technologies to cost effectively bring these technologies to market. We describe an ultra-clean (low leak rate) wafer-level vacuum encapsulation microfabrication process of Micro-Electro-Mechanical Systems (MEMS) based sensors and devices. Using this process we have fabricated inertial sensors, frequency reference resonators, and pressure sensors. In addition to providing excellent resistance to shock and vibration, this combined microfabrication and packaging method would allow the use of high volume low cost plastic packaging at the device level. The microfabrication process is an 8” wafer process based on high aspect ratio bulk micromachining of a 30 μm thick single-crystal silicon device layer that is vacuum encapsulated at 10 mTorr between two silicon wafers with the demonstrated leak rate of only 6.5 × 10−18 atm cm3/s.

Wafer Bonding Processes for the Manufacture of Microsystems

2008 ◽  
Author(s):  
Tony Rogers ◽  
Nick Aitken
Keyword(s):  
Bond Strength ◽  
Wafer Bonding ◽  
High Efficiency ◽  
Glass Frit ◽  
Acoustic Microscopy ◽  
Anodic Bonding ◽  
High Yield ◽  
Mems Devices ◽  
Wafer Level ◽  
Wafer Level Packaging

Wafer bonding is a widely used step in the manufacture of Microsystems, and serves several purposes: • Structural component of the MEMS device. • First level packaging. • Encapsulation of vacuum or controlled gas. In addition the technology is becoming more widely used in IC fabrication for wafer level packaging (WLP) and 3D integration. It is also widely used for the fabrication of micro fluidic structures and in the manufacture of high efficiency LED’s. Depending on the application, temperature constraints, material compatibility etc. different wafer bonding processes are available, each with their own benefits and drawbacks. This paper describes various wafer bonding processes that are applicable, not only to silicon, but other materials such as glass and quartz that are commonly used in MEMS devices. The process of selecting the most appropriate bonding process for the particular application is presented along with examples of anodic, glass frit, eutectic, direct, adhesive and thermo-compression bonding. The examples include appropriate metrology for bond strength and quality. The paper also addresses the benefits of being able to treat the wafer surfaces in-situ prior to bonding in order to improve yield and bond strength, and also discusses equipment requirements for achieving high yield wafer bonding, along with high precision alignment accuracy, good force and temperature uniformity, high wafer throughput, etc. Some common problems that can affect yield are identified and discussed. These include local temperature variations, that can occur with anodic bonding, and how to eliminate them; how to cope with materials of different thermal expansion coefficient; how best to deal with out-gassing and achieve vacuum encapsulation; and procedures for multi-stacking wafers of differing thicknesses. The presentation includes infra-red and scanning acoustic microscopy images of various bond types, plus some examples of what can go wrong if the correct manufacturing protocol is not maintained.

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