scholarly journals QUANTUM SIMULATIONS OF DUAL GATE MOSFET DEVICES: BUILDING AND DEPLOYING COMMUNITY NANOTECHNOLOGY SOFTWARE TOOLS ON NANOHUB.ORG

2007 ◽  
Vol 17 (03) ◽  
pp. 485-494 ◽  
Author(s):  
SHAIKH AHMED ◽  
GERHARD KLIMECK ◽  
DERRICK KEARNEY ◽  
MICHAEL MCLENNAN ◽  
M. P. ANANTRAM
Keyword(s):  
High Performance ◽  
Short Channel ◽  
Web Based ◽  
Simulation Tools ◽  
Channel Effects ◽  
Dual Gate ◽  
Quantum Mechanical Effects ◽  
And Performance ◽  
Device Properties ◽  
The Impact

Undesirable short-channel effects associated with the relentless downscaling of conventional CMOS devices have led to the emergence of new classes of MOSFETs. This has led to new and unprecedented challenges in computational nanoelectronics. The device sizes have already reached the level of tens of nanometers where quantum nature of charge-carriers dominates the device operation and performance. The goal of this paper is to describe an on-going initiative on nanoHUB.org to provide new models, algorithms, approaches, and a comprehensive suite of freely-available web-based simulation tools for nanoscale devices with capabilities not yet available commercially. Three software packages nanoFET, nanoMOS and QuaMC are benchmarked in the simulation of a widely-studied high-performance novel MOSFET device. The impact of quantum mechanical effects on the device properties is elucidated and key design issues are suggested.

Design Considerations for Robust Manufacturing and High Yield of 1.2 kV 4H-SiC VDMOS Transistors

2019 ◽  
Vol 963 ◽  
pp. 763-767
Author(s):  
Holger Schlichting ◽  
Tomasz Sledziewski ◽  
Anton Bauer ◽  
Tobias Erlbacher
Keyword(s):  
High Performance ◽  
Electrical Characteristic ◽  
Semiconductor Device ◽  
Critical Length ◽  
Channel Length ◽  
High Yield ◽  
Short Channel ◽  
Channel Effects ◽  
Small Change ◽  
The Impact

Production yield is a major factor for semiconductor device manufacturing. To produce high performance devices cost efficiently, it is important to know the process windows of the implemented production technology. This can influence the yield in different ways. One of the critical steps is the photolithography. In this work the impact of misalignment within the technological limits is analyzed and discussed. 4H-SiC VDMOS Transistors were produced and the electrical characteristics were compared with the overlay accuracy of the devices. Small change in channel length can lead to large impact on the electrical characteristic. Especially when the channel length reaches values near to the critical length for short channel effects (SCEs), small overlay inaccuracies influence the electrical characteristic of the devices in an increasing manner. Different cell designs were analyzed regarding their robustness to misalignment.

Monte Carlo study of 50 nm-long single and dual-gate MODFETs: suppression of short-channel effects

1993 ◽  
Vol 3 (9) ◽  
pp. 1719-1728
Author(s):  
P. Dollfus ◽  
P. Hesto ◽  
S. Galdin ◽  
C. Brisset
Keyword(s):  
Monte Carlo ◽  
Monte Carlo Study ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
Dual Gate

scholarly journals The Impact of Organizational Culture and Performance Work System on Employees’ Performance

2018 ◽  
Vol 11 (6) ◽  
pp. 199 ◽  
Author(s):  
Amirreza Salehipour ◽  
Abdollah Ah mand
Keyword(s):  
Organizational Culture ◽  
High Performance ◽  
Ministry Of Education ◽  
Work System ◽  
Strong Relation ◽  
High Performance Work System ◽  
Research Questions ◽  
And Performance ◽  
The Impact ◽  
The Given

Necessity of improving employees’ performance in ministry of education in Iran was the reason of conducting this research. Authors are focused on the impact of High Performance Work System (HPWS) and the culture of organization on employees’ performance in Iran ministry of education. By conducting specified study based on distributed survey questionnaire to 162 members of ministry of education in Iran, this study aims to provide answer to the given research questions of study. The outcome of hypotheses testing illustrate HPWS significantly effects ministry members’ performance and shows strong relation between variables. Likewise, organizational culture demonstrates significant affirmative impact on Iran ministry of education members and employees’ performance. Findings of current research indicate that the ministry of education in Iran requires immediate action toward improving performance of members to obtain desired outcome. Accordingly, to the result of present study, current research attempts to provide practical concepts and illustrate limitations, suggestions for improvement of ministry and future study in this field.

ACR-1000™ Fuel Design Verification

2010 ◽  
Author(s):  
David J. Wren ◽  
Patrick Reid ◽  
Len L. Wright
Keyword(s):  
High Performance ◽  
Reactor Core ◽  
Cold Test ◽  
Performance Criteria ◽  
Extensive Experience ◽  
Fuel Bundle ◽  
Test Loop ◽  
Fuel Design ◽  
And Performance ◽  
The Impact

The ACR-1000™ design is an evolutionary advancement of the proven CANDU® reactor design that delivers enhanced economic performance, safety, operability and maintainability. The fuel for the ACR-1000 design is based on the well established CANDU fuel bundle design that has over 40 years of demonstrated high performance. Building on its extensive experience in fuel design and analysis, and fuel testing, AECL has designed a CANFLEX-ACR™ fuel bundle that incorporates the latest improvements in CANDU fuel bundle design. The ACR-1000 fuel bundle also includes features that enable the ACR-1000 to achieve higher fuel burn-up and improved reactor core physics characteristics. To verify that the CANFLEX-ACR fuel bundle design will meet and exceed all design requirements, an extensive program of design analysis and testing is being carried out. This program rigorously evaluates the ability of the fuel design to meet all design and performance criteria and particularly those related to fuel failure limits. The design analyses address all of the phenomena that affect the fuel during its residence in the reactor core. Analysis is performed using a suite of computer codes that are used to evaluate the temperatures, deformations, stresses and strains experienced by the fuel bundle during its residence in the reactor core. These analyses take into account the impact of fuel power history and core residence time. Complementing the analyses, testing is performed to demonstrate the compatibility of the fuel with the reactor heat transport system and fuel handling systems, and to demonstrate the ability of the fuel to withstand the mechanical forces that it will experience during its residence in the core. The testing program includes direct measurement of prototype fuel element and fuel bundle properties and performance limits. A number of different test facilities are used including a cold test loop and a hot test loop with a full-scale ACR-1000 fuel channel that operates at reactor coolant temperatures, pressures and flows. This paper summarizes the out-reactor test program and related analysis that provide the basis for verifying that the ACR-1000 fuel design meets its requirements.

scholarly journals Performance Measures of Different Gate Oxide Materials in Gate All Around Fet

2020 ◽  
Vol 9 (2) ◽  
pp. 23-25
Keyword(s):  
High Performance ◽  
Field Effect Transistors ◽  
Gate Oxide ◽  
Oxide Semiconductor ◽  
Oxide Materials ◽  
Performance Limits ◽  
Short Channel ◽  
Advanced Technique ◽  
And Performance

The classical planar Metal Oxide Semiconductor Field Effect Transistors (MOSFET) is fabricated by oxidation of a semiconductor namely Silicon. In this generation, an advanced technique called 3D system architecture FETs, are introduced for high performance and low power quality of devices. Based on the limitations of Short Channel Effect (SCE), Silicon (Si) FET cannot be scaled under 10nm. Hence various performing measures like methods, principles, and geometrics are done to upscale the semiconductor. CMOS using alternate channel materials like GE and III-Vs on substrates is a highly anticipated technique for developing nanowire structures. By considering these issues, in this paper, we developed a simulation model that provides accurate results basing on Gate layout and multi-gate NW FET's so that the scaling can be increased few nanometers long and performance limits gradually increases. The model developed is SILVACO that tests the action of FET with different gate oxide materials.

A computational prototyping environment interface for DoD CREATE™-AV Helios simulations

2021 ◽  
Author(s):  
Robert Haehnel ◽  
Scott Christensen ◽  
J. Whitlow ◽  
Andrew Bauer ◽  
Ari Meyer ◽  
...  
Keyword(s):  
Time Series ◽  
Modeling And Simulation ◽  
High Performance Computing ◽  
Department Of Defense ◽  
High Performance ◽  
Data Input ◽  
Web Based ◽  
Simulation Tools ◽  
Parametric Studies ◽  
Performance Computing

Computational Prototyping Environment (CPE) is a web-based portal designed to simplify running Department of Defense (DoD) modeling and simulation tools on the DoD Supercomputing Resource Center’s (DSRC) High Performance Computing (HPC) systems. The first of these tools to be deployed in the CPE is an application (app) to conduct parametric studies and view results using the CREATE-AV Helios CFD software. Initial capability includes hover (collective sweep) and forward flight (speed sweep) performance calculations. The CPE Helios app allows for job submission to a DSRC’s HPC system and for the viewing of results created by Helios, i.e., time series and volumetric data. Example data input and results viewing are presented. Planned future functionality is also outlined.

Comparative Performance Analysis of Nanowire and Nanotube Field Effect Transistors

2021 ◽  
pp. 54-70
Author(s):  
Raj Kumar ◽  
Shashi Bala ◽  
Arvind Kumar
Keyword(s):  
Performance Analysis ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Ballistic Transport ◽  
High Mobility ◽  
Short Channel Effects ◽  
Short Channel ◽  
Comparative Performance ◽  
Channel Effects ◽  
And Performance

To have enhanced drive current and diminish short channel effects, planer MOS transistors have migrated from single-gate devices to three-dimensional multi-gate MOSFETs. The gate-all-around nanowire field-effect transistor (GAA NWFET) and nanotube or double gate-all-around field-effect transistors (DGGA-NTFET) have been proposed to deal with short channel effects and performance relates issues. Nanowire and nanotube-based field-effect transistors can be considered as leading candidates for nanoscale devices due to their superior electrostatic controllability, and ballistic transport properties. In this work, the performance of GAA NWFETs and DGAA-NT FETs will be analyzed and compared. III-V semiconductor materials as a channel will also be employed due to their high mobility over silicon. Performance analysis of junctionless nanowire and nanotube FETs will also be compared and presented.

scholarly journals Extremely high-gain source-gated transistors

2019 ◽  
Vol 116 (11) ◽  
pp. 4843-4848 ◽  
Author(s):  
Jiawei Zhang ◽  
Joshua Wilson ◽  
Gregory Auton ◽  
Yiming Wang ◽  
Mingsheng Xu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Indium Tin Oxide ◽  
High Performance ◽  
Critical Factor ◽  
High Gain ◽  
Oxide Semiconductor ◽  
Design Rule ◽  
Short Channel ◽  
Channel Effects ◽  
Channel Lengths

Despite being a fundamental electronic component for over 70 years, it is still possible to develop different transistor designs, including the addition of a diode-like Schottky source electrode to thin-film transistors. The discovery of a dependence of the source barrier height on the semiconductor thickness and derivation of an analytical theory allow us to propose a design rule to achieve extremely high voltage gain, one of the most important figures of merit for a transistor. Using an oxide semiconductor, an intrinsic gain of 29,000 was obtained, which is orders of magnitude higher than a conventional Si transistor. These same devices demonstrate almost total immunity to negative bias illumination temperature stress, the foremost bottleneck to using oxide semiconductors in major applications, such as display drivers. Furthermore, devices fabricated with channel lengths down to 360 nm display no obvious short-channel effects, another critical factor for high-density integrated circuits and display applications. Finally, although the channel material of conventional transistors must be a semiconductor, by demonstrating a high-performance transistor with a semimetal-like indium tin oxide channel, the range and versatility of materials have been significantly broadened.

A New Approach to the Characteristics and Short-Channel Effects of Double-Gate Carbon Nanotube Field-Effect Transistors using MATLAB: A Numerical Study

2012 ◽  
Vol 67 (6-7) ◽  
pp. 317-326 ◽  
Author(s):  
Alireza Heidari ◽  
Niloofar Heidari ◽  
Foad Khademi Jahromi ◽  
Roozbeh Amiri ◽  
Mohammadali Ghorbani
Keyword(s):  
Carbon Nanotube ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Open Boundary ◽  
Double Gate ◽  
Short Channel Effects ◽  
Drain Voltage ◽  
Short Channel ◽  
Channel Effects ◽  
The Impact

In this paper, first, the impact of different gate arrangements on the short-channel effects of carbon nanotube field-effect transistors with doped source and drain with the self-consistent solution of the three-dimensional Poisson equation and the Schr¨odinger equation with open boundary conditions, within the non-equilibrium Green function, is investigated. The results indicate that the double-gate structure possesses a quasi-ideal subthreshold oscillation and an acceptable decrease in the drain induced barrier even for a relatively thick gate oxide (5 nm). Afterward, the electrical characteristics of the double-gate carbon nanotube field-effect transistors (DG-CNTFET) are investigated. The results demonstrate that an increase in diameter and density of the nanotubes in the DG-CNTFET increases the on-state current. Also, as the drain voltage increases, the off-state current of the DG-CNTFET decreases. In addition, regarding the negative gate voltages, for a high drain voltage, increasing in the drain current due to band-to-band tunnelling requires a larger negative gate voltage, and for a low drain voltage, resonant states appear

CMOS DEVICES ARCHITECTURES AND TECHNOLOGY INNOVATIONS FOR THE NANOELECTRONICS ERA

2006 ◽  
Vol 16 (01) ◽  
pp. 193-219 ◽  
Author(s):  
S. DELEONIBUS ◽  
B. de SALVO ◽  
T. ERNST ◽  
O. FAYNOT ◽  
T. POIROUX ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Gate Dielectric ◽  
Low Voltage ◽  
Short Channel Effects ◽  
Short Channel ◽  
Trade Offs ◽  
Future System ◽  
The Future ◽  
Channel Effects

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials ( Ge , diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.

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