SOI Technologies from Microelectronics to Microsystems — Meeting the More than Moore Roadmap Requirements

2016 ◽  
Vol 25 (01n02) ◽  
pp. 1640004
Author(s):  
Jean-Pierre Raskin
Keyword(s):  
High Frequency ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Harsh Environments ◽  
High Resistivity ◽  
Sensors And Actuators ◽  
Thin Film Sensors ◽  
Temperature Radiation ◽  
Commercial Applications ◽  
Soi Technology

This last decade Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency, reaching cut-off frequencies close to 500 GHz for nMOSFETs, and for harsh environments (high temperature, radiation) commercial applications. SOI also presents high resistivity substrate capabilities, leading to substantially reduced substrate losses and non-linearities. More recently, SOI technology has been emerging as a major contender for heterogeneous microsystems applications. In this work, we demonstrate the advantages of SOI technology for Radio Frequency CMOS integration as well as for building thin film sensors on thin dielectric membrane and three-dimensional micro-electro-mechanical (MEMS) sensors and actuators cointegrated with their associated SOI CMOS circuitry.

Three-Dimensional Integration Technology for Advanced Focal Planes

2008 ◽  
Vol 1112 ◽  
Author(s):  
Craig Lewis Keast ◽  
Brian Aull ◽  
James Burns ◽  
Chenson Chen ◽  
Jeff Knecht ◽  
...  
Keyword(s):  
Focal Plane ◽  
Three Dimensional ◽  
Focal Plane Arrays ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
Integration Technology ◽  
Electrical Interconnection ◽  
Circuit Integration ◽  
Micrometer Scale ◽  
Soi Technology

AbstractWe have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.

Application of FIB Circuit Edit in Analysis of Memory Failure of SOI Devices

2006 ◽  
Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
First Case ◽  
Edx Analyses ◽  
Memory Failure ◽  
Soi Devices ◽  
Voltage Contrast ◽  
Soi Technology

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.

scholarly journals A RF Redundant TSV Interconnection for High Resistance Si Interposer

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 169
Author(s):  
Mengcheng Wang ◽  
Shenglin Ma ◽  
Yufeng Jin ◽  
Wei Wang ◽  
Jing Chen ◽  
...  
Keyword(s):  
Millimeter Wave ◽  
High Frequency ◽  
High Performance ◽  
Rapid Development ◽  
Coplanar Waveguide ◽  
Equivalent Circuit Model ◽  
High Resistivity ◽  
Performance Requirements ◽  
Wave Radar ◽  
Interconnect Design

Through Silicon Via (TSV) technology is capable meeting effective, compact, high density, high integration, and high-performance requirements. In high-frequency applications, with the rapid development of 5G and millimeter-wave radar, the TSV interposer will become a competitive choice for radio frequency system-in-package (RF SIP) substrates. This paper presents a redundant TSV interconnect design for high resistivity Si interposers for millimeter-wave applications. To verify its feasibility, a set of test structures capable of working at millimeter waves are designed, which are composed of three pieces of CPW (coplanar waveguide) lines connected by single TSV, dual redundant TSV, and quad redundant TSV interconnects. First, HFSS software is used for modeling and simulation, then, a modified equivalent circuit model is established to analysis the effect of the redundant TSVs on the high-frequency transmission performance to solidify the HFSS based simulation. At the same time, a failure simulation was carried out and results prove that redundant TSV can still work normally at 44 GHz frequency when failure occurs. Using the developed TSV process, the sample is then fabricated and tested. Using L-2L de-embedding method to extract S-parameters of the TSV interconnection. The insertion loss of dual and quad redundant TSVs are 0.19 dB and 0.46 dB at 40 GHz, respectively.

LOW-NOISE SILICON-ON-INSULATOR HALL DEVICES

2004 ◽  
Vol 04 (02) ◽  
pp. L345-L354 ◽  
Author(s):  
Y. HADDAB ◽  
V. MOSSER ◽  
M. LYSOWEC ◽  
J. SUSKI ◽  
L. DEMEUS ◽  
...  
Keyword(s):  
Noise Level ◽  
Low Voltage ◽  
Silicon Layer ◽  
Electrical Current ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Technological Parameters ◽  
Wide Range ◽  
Hall Sensors ◽  
Soi Technology

Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring the useful range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.

Open-Source Real-Time Robot Operation and Control System for Highly Dynamic, Modular Machines

2013 ◽  
Author(s):  
Andrew Peekema ◽  
Daniel Renjewski ◽  
Jonathan Hurst
Keyword(s):  
Control System ◽  
Open Source ◽  
Real Time ◽  
High Frequency ◽  
Performance Test ◽  
Frequency Control ◽  
Human Robot Interaction ◽  
Sensors And Actuators ◽  
Key Innovation ◽  
Hard Real Time

The control system of a highly dynamic robot requires the ability to respond quickly to changes in the robot’s state. This type of system is needed in varying fields such as dynamic locomotion, multicopter control, and human-robot interaction. Robots in these fields require software and hardware capable of hard real-time, high frequency control. In addition, the application outlined in this paper requires modular components, remote guidance, and mobile control. The described system integrates a computer on the robot for running a control algorithm, a bus for communicating with microcontrollers connected to sensors and actuators, and a remote user interface for interacting with the robot. Current commercial solutions can be expensive, and open source solutions are often time consuming. The key innovation described in this paper is the building of a control system from existing — mostly open source — components that can provide realtime, high frequency control of the robot. This paper covers the development of such a control system based on ROS, OROCOS, and EtherCAT, its implementation on a dynamic bipedal robot, and system performance test results.

Development of Thin Metal Film Deposition Process for the Intravascular Catheter

1999 ◽  
Author(s):  
Seok Chung ◽  
Jun Keun Chang ◽  
Dong Chul Han
Keyword(s):  
Metal Film ◽  
Three Dimensional ◽  
Deposition Process ◽  
Medical Application ◽  
Thin Metal Film ◽  
Film Deposition ◽  
Thin Metal ◽  
Mems Devices ◽  
Sensors And Actuators ◽  
Custom Made

Abstract To make some MF.MS devices such as sensors and actuators be useful in the medical application, it is required to integrate this devices with power or sensor lines and to keep the hole devices biocompatible. Integrating micro machined sensors and actuators with conventional copper lines is incompatible because the thin copper lines are not easy to handle in the mass production. To achieve the compatibility of wiring method between MEMS devices, we developed the thin metal film deposition process that coats micropattered thin copper films on the non silicon-wafer substrate. The process was developed with the custom-made three-dimensional thin film sputter/evaporation system. The system consists of process chamber, two branch chambers, substrate holder unit and linear/rotary motion feedthrough. Thin metal film was deposited on the biocompatible polymer, polyurethane (PellethaneR) and silicone, catheter that is 2 mm in diameter and 1,000 mm in length. We deposited Cr/Cu and Ti/Cu layer and made a comparative study of the deposition processes, sputtering and evaporation. The temperature of both the processes were maintained below 100°C, for the catheter not melting during the processes. To use the films as signal lines connect the signal source to the actuator on the catheter tip, we machined the films into desired patterns with the eximer laser. In this paper, we developed the thin metal film deposition system and processes for the biopolymeric substrate used in the medical MEMS devices.

STUDY OF ELECTRICAL CHARACTERISTIC FOR 50NM AND 10NM SOI BODY THICKNESS IN MOSFET DEVICE

2015 ◽  
Vol 77 (21) ◽  
Author(s):  
M.N.I.A Aziz ◽  
F. Salehuddin ◽  
A.S.M. Zain ◽  
K.E. Kaharudin
Keyword(s):  
Thin Film ◽  
Electrical Characteristic ◽  
Silicon On Insulator ◽  
Electrical Characteristics ◽  
Short Channel ◽  
Doping Density ◽  
Soi Mosfet ◽  
Buried Oxide ◽  
Soi Technology ◽  
Better Than

Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effect (SCE) problems. The SOI is believed to be capable of suppressing the SCE, thereby improving the overall electrical characteristics of MOSFET device. SCE in SOI MOSFET is heavily influenced by thin film thickness, thin-film doping density and buried oxide (BOX) thickness. This paper will analyze the effect of BOX towards SOI MOSFET device. The 50nm and 10nm thickness of buried oxide in SOI MOSFET was developed by using SILVACO TCAD tools, specifically known as Athena and Atlas modules. From the observation, the electrical characteristic of 100nm thickness is slightly better than 50nm and 10nm. It is observed that the value drive current of 10nm and 100nm thickness SOI MOSFET was 6.9% and 11% lower than 50nm respectively, but the overall 50nm is superior. However, the electrical characteristics of 10nm SOI MOSFET are still closer and within the range of ITRS 2013 prediction.

scholarly journals Intermetallic REPtZn Compounds with TiNiSi-type Structure

2011 ◽  
Vol 66 (7) ◽  
pp. 671-676 ◽  
Author(s):  
Trinath Mishra ◽  
Rainer Pöttgen
Keyword(s):  
Rare Earth ◽  
Single Crystal ◽  
Coordination Number ◽  
High Frequency ◽  
Three Dimensional ◽  
Type Structure ◽  
Rare Earth Compounds ◽  
Crystal Data ◽  
X Ray Diffraction ◽  
X Ray

The equiatomic rare earth compounds REPtZn (RE = Y, Pr, Nd, Gd-Tm) were synthesized from the elements in sealed tantalum tubes by high-frequency melting at 1500 K followed by annealing at 1120 K and quenching. The samples were characterized by powder X-ray diffraction. The structures of four crystals were refined from single-crystal diffractometer data: TiNiSi type, Pnma, a = 707.1(1), b = 430.0(1), c = 812.4(1) pm, wR2 = 0.066, 602 F2, 21 variables for PrPt1.056Zn0.944; a = 695.2(1), b = 419.9(1), c = 804.8(1) pm, wR2 = 0.041, 522 F2, 21 variables for GdPt0.941Zn1.059; a = 688.2(1), b = 408.1(1), c = 812.5(1) pm, wR2 = 0.041, 497 F2, 22 variables for HoPt1.055Zn0.945; a = 686.9(1), b = 407.8(1), c = 810.4(1) pm, wR2 = 0.061, 779 F2, 20 variables for ErPtZn. The single-crystal data indicate small homogeneity ranges REPt1±xZn1±x. The platinum and zinc atoms build up three-dimensional [PtZn] networks (265 - 269 pm Pt-Zn in ErPtZn) in which the erbium atoms fill cages with coordination number 16 (6 Pt + 6 Zn + 4 Er). Bonding of the erbium atoms to the [PtZn] network proceeds via shorter RE-Pt distances, i. e. 288 - 293 pm in ErPtZn.

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