A 0.2–3.3 GHz 2.4 dB NF 45 dB gain CMOS current-mode receiver front-end

2020 ◽  
Vol 34 (22) ◽  
pp. 2050226
Author(s):  
Benqing Guo ◽  
Jing Gong ◽  
Yao Wang ◽  
Jingwei Wu
Keyword(s):  
Power Efficiency ◽  
Supply Voltage ◽  
Current Mode ◽  
Fully Differential ◽  
Cmos Scaling ◽  
Front End ◽  
Gaas Devices ◽  
Comparable Performance ◽  
Common Gate ◽  
Scaling Down

A CMOS fully differential current-mode front-end for SAW-less receivers is proposed. The noise-canceling LNTA has a main path of the common-gate (CG) stage and an auxiliary path of the inverter stage. A current mirror is used to combine the signals from the main and auxiliary paths in current mode. The stacked nMOS/pMOS configurations improve their power efficiency. The traditional stacked tri-state inverter as D-latch replaced by the discrete inverter and transmission gate enables a reduced supply voltage of divider core. LO generator based on the improved divider provides quarter LO signals to drive the proposed LNTA-shared receiver front-end. Simulation results in 180 nm CMOS indicate that the integrated receiver front-end provides an NF of 2.4 dB, and a maximum gain of 45 dB from 0.2 to 3.3 GHz. The in-band (IB) and out-of-band (OB) IIP3 of 2.5 dBm and 4 dBm, are obtained, respectively. With CMOS scaling down continuously, CMOS devices are providing increased transit frequency and reduced intrinsic parasitics which are important for radio frequency (RF) and millimeter-wave applications. As a promising solution, CMOS RF delivers comparable performance to silicon bipolar and GaAs devices but at a much lower cost and higher integration level. Supply voltage reduction with CMOS scaling down also poses a stringent linearity requirement. Avoiding the conventional trade-off between the supply voltage and linearity headroom, the proposed receiver front-end based on the current mode principle is with weak linearity dependency on the supply voltage and provides excellent anti-blocker interference capability.

scholarly journals A low-voltage CMOS current-mode differential front-end for optical communications

2021 ◽  
Author(s):  
Bendong Sun
Keyword(s):  
Optical Communications ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Building Blocks ◽  
Switching Noise ◽  
Current Feedback ◽  
Fully Differential ◽  
Digital Circuitry

This thesis deals with the design of a low-voltage fully-differential CMOS current-mode preamplifier for optical communications. An in-depth comparative analysis of the building blocks of low-voltage CMOS current-mode circuits is carried out. Two new bandwidth enhancement techniques, namely inductor series-peaking and current feedback, are introduced and implemented in the design. The feedback also reduces the value of the series-peaking inductor. The minimum supply voltage of the amplifier is only one threshold voltage plus one pinch-off voltage. The preamplifier has a balanced differential topology such that the effect of bias dependent mismatches is minimized and the amplifier is insensitive to the switching noise caused by the digital circuitry. Negative differential current feedbacks are implemented to boost the bandwidth and increase the dynamic range.

Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End

2006 ◽  
Author(s):  
Antonio Liscidini ◽  
Cesare Ghezzi ◽  
Emanuele Depaoli ◽  
Guido Albasini ◽  
Ivan Bietti ◽  
...  
Keyword(s):  
Current Mode ◽  
Rf Cmos ◽  
Front End ◽  
Common Gate ◽  
Transformer Feedback

scholarly journals A low-voltage CMOS current-mode differential front-end for optical communications

2021 ◽  
Author(s):  
Bendong Sun
Keyword(s):  
Optical Communications ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Building Blocks ◽  
Switching Noise ◽  
Current Feedback ◽  
Fully Differential ◽  
Digital Circuitry

This thesis deals with the design of a low-voltage fully-differential CMOS current-mode preamplifier for optical communications. An in-depth comparative analysis of the building blocks of low-voltage CMOS current-mode circuits is carried out. Two new bandwidth enhancement techniques, namely inductor series-peaking and current feedback, are introduced and implemented in the design. The feedback also reduces the value of the series-peaking inductor. The minimum supply voltage of the amplifier is only one threshold voltage plus one pinch-off voltage. The preamplifier has a balanced differential topology such that the effect of bias dependent mismatches is minimized and the amplifier is insensitive to the switching noise caused by the digital circuitry. Negative differential current feedbacks are implemented to boost the bandwidth and increase the dynamic range.

scholarly journals Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits

2014 ◽  
Vol 2014 ◽  
pp. 1-10 ◽  
Author(s):  
Ruiping Cao ◽  
Jianping Hu
Keyword(s):  
Optimization Algorithm ◽  
High Speed ◽  
Supply Voltage ◽  
Current Mode ◽  
Good Alternative ◽  
Model Parameters ◽  
In Series ◽  
Scaling Down ◽  
Power Delay Product ◽  
Near Threshold

In high-speed applications, MOS current mode logic (MCML) is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP). However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML) circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.

A LOW-POWER LOW-VOLTAGE 6-BIT 1.33 GS/s FULLY MCML ALL NMOS FLASH ADC WITHOUT A FRONT-END T/H

2013 ◽  
Vol 22 (08) ◽  
pp. 1350074 ◽  
Author(s):  
SARA NESHANI ◽  
SEYED JAVAD AZHARI
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Low Voltage ◽  
Current Mode ◽  
Flash Adc ◽  
Analog To Digital ◽  
Current Mode Logic ◽  
Front End ◽  
Compact Size ◽  
Nmos Transistors

In this work, a 6-bit 1.33 GS/s flash analog-to-digital converter (ADC) is proposed. To noticeably save the power and area and greatly increase the speed, compactness and accuracy its complete structure is elaborately implemented in MOS Current Mode Logic (MCML) topology. The proposed ADC does not use a front-end track and hold (T/H) block either. Furthermore, a novel optimized resistance ratio averaging-interpolation scheme is applied to: (1) reduce the offset, nonlinearity, number of preamplifiers, area and the power (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is completely built by NMOS transistors realizing the ever desired unique NMCML (NMOS-MCML) structure. Using intermediate gray encoding and exponential gains by extra latches greatly removes the bubble/meta-stability error and increases both the speed and the accuracy. Utilizing a differential ladder and some other deliberate arrangements reduces the kickback noise and common mode interferences, minimizes the structure and facilitates fast recovery of overdrive signals. The proposed ADC is simulated by Hspice using 0.18 μm TSMC technology and shows; effective resolution band width (ERBW) larger than 903 MHz that is 1.36 times more than Nyquist frequency (fs/2), 35.17 dB/49.4 dB SNDR/SFDR, 5.53 bits ENOB (rather flat SNDR and ENOB from 50 MHz to 750 MHz), and the low power consumption of 37.77 mW from a 1.2 V supply. These results prove that applying so many effective and novel plans has obtained a unique all N-MCML flash ADC with power-efficiency of 0.61 pJ per conversion step. Both Monte Carlo and corner cases simulations in addition to temperature analysis are performed that prove both intra-die and inter-die robustness of the proposed structure.

scholarly journals An 87% Power-Efficiency Hybrid of Voltage- and Current-Mode Line Driver with an Adaptive Amplitude Tuning

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1785
Author(s):  
Changjoo Park ◽  
Minjae Lee
Keyword(s):  
Power Efficiency ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Current Mode ◽  
Total Power ◽  
Area Network ◽  
Signal Attenuation ◽  
Load Impedance ◽  
Total Power Consumption ◽  
Line Driver

This brief presents a hybrid of voltage- and current-mode line drivers for the turbo controller area network (CAN). The current-mode scheme prevents signal attenuation caused by source termination resistors, and it enhances signal power efficiency. On top of that, an adaptive amplitude tuning is implemented to mitigate non-linearity and closed-loop gain variations against load impedance variations. The proposed line driver achieves 87.0% power-efficiency and total harmonic distortion, plus noise (THD+N) of −49.0 dB at an input frequency of 40 MHz and output swing of 2.8 VPP differential. The adaptive amplitude tuning allows load impedance variations from 80 Ω to 160 Ω. The total power consumption is 37.6 mW with a 1.8 V supply voltage in 180 nm CMOS, and it occupies 0.377 mm2.

A biasing based current mode analog front-end for biomedical applications

2021 ◽  
Author(s):  
Raja Krishnamoorthy ◽  
E. Kavitha ◽  
V. Beslin Geo ◽  
K.S.R. Radhika ◽  
C. Bharatiraja
Keyword(s):  
Biomedical Applications ◽  
Current Mode ◽  
Front End ◽  
Analog Front End

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Sign in / Sign up

Export Citation Format

Share Document