scholarly journals An 87% Power-Efficiency Hybrid of Voltage- and Current-Mode Line Driver with an Adaptive Amplitude Tuning

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1785
Author(s):  
Changjoo Park ◽  
Minjae Lee
Keyword(s):  
Power Efficiency ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Current Mode ◽  
Total Power ◽  
Area Network ◽  
Signal Attenuation ◽  
Load Impedance ◽  
Total Power Consumption ◽  
Line Driver

This brief presents a hybrid of voltage- and current-mode line drivers for the turbo controller area network (CAN). The current-mode scheme prevents signal attenuation caused by source termination resistors, and it enhances signal power efficiency. On top of that, an adaptive amplitude tuning is implemented to mitigate non-linearity and closed-loop gain variations against load impedance variations. The proposed line driver achieves 87.0% power-efficiency and total harmonic distortion, plus noise (THD+N) of −49.0 dB at an input frequency of 40 MHz and output swing of 2.8 VPP differential. The adaptive amplitude tuning allows load impedance variations from 80 Ω to 160 Ω. The total power consumption is 37.6 mW with a 1.8 V supply voltage in 180 nm CMOS, and it occupies 0.377 mm2.

scholarly journals Towards Realization of a Low-Voltage Class-AB VCII with High Current Drive Capability

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2303
Author(s):  
Leila Safari ◽  
Gianluca Barile ◽  
Vincenzo Stornelli ◽  
Shahram Minaei ◽  
Giuseppe Ferri
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Current Drive ◽  
Total Power ◽  
High Signal ◽  
High Current ◽  
Class Ab ◽  
Total Power Consumption

In this paper, the implementation of a low-voltage class AB second generation voltage conveyor (VCII) with high current drive capability is presented. Simple realization and good overall performance are the main features of the proposed circuit. Proper solutions and techniques were used to achieve high signal swing and high linearity at Y, X and Z ports of VCII as well as low-voltage operation. The operation of the proposed VCII was verified through SPICE simulations based on TSMC 0.18 µm CMOS technology parameters and a supply voltage of ±0.9 V. The small signal impedance values were 973 Ω, 120 kΩ and 217 Ω at Y, X and Z ports, respectively. The maximum current at the X port was ±10 mA with maximum total harmonic distortion (THD) of 2.4% at a frequency of 1 MHz. Considering a bias current (IB) of 29 µA and output current at the X port (IX) of 10 mA, the current drive capability (IX/IB) of about 345 was achieved at the X port. The voltage swing at the Z port was (−0.4, 0.4) V. The THD value at the Z port for an input signal with 0.8 V peak-to-peak value and frequency of 1 MHz was 3.9%. The total power consumption was 0.393 µW.

scholarly journals 1.5-V CMOS Current Multiplier/Divider

2018 ◽  
Vol 8 (3) ◽  
pp. 1478 ◽  
Author(s):  
Jetsdaporn Satansup ◽  
Worapong Tangsrirat
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Total Power ◽  
Total Power Consumption ◽  
Linearity Error ◽  
Low Supply Voltage ◽  
Circuit Technique

A circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented.  It is based on the use of a compact current quadratic cell able to operate at low supply voltage.  The proposed circuit is designed and simulated for implementing in TSMC 0.25-m CMOS technology with a single supply voltage of 1.5 V.  Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 W, and -3dB small-signal frequency of about 245 MHz.

scholarly journals A Novel Differential Log-Companding Amplifier for Biosignal Sensing

2016 ◽  
Vol 2016 ◽  
pp. 1-7
Author(s):  
Zigang Dong ◽  
Xiaolin Zhou ◽  
Yuanting Zhang
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Nonlinear Function ◽  
New Method ◽  
Total Power ◽  
Maximum Output ◽  
Output Current ◽  
Current Range ◽  
Symmetrical Configuration ◽  
Total Power Consumption

We proposed a new method for designing the CMOS differential log-companding amplifier which achieves significant improvements in linearity, common-mode rejection ratio (CMRR), and output range. With the new nonlinear function used in the log-companding technology, this proposed amplifier has a very small total harmonic distortion (THD) and simultaneously a wide output current range. Furthermore, a differential structure with conventionally symmetrical configuration has been adopted in this novel method in order to obtain a high CMRR. Because all transistors in this amplifier operate in the weak inversion, the supply voltage and the total power consumption are significantly reduced. The novel log-companding amplifier was designed using a 0.18 μm CMOS technology. Improvements in THD, output current range, noise, and CMRR are verified using simulation data. The proposed amplifier operates from a 0.8 V supply voltage, shows a 6.3 μA maximum output current range, and has a 6 μW power consumption. The THD is less than 0.03%, the CMRR of this circuit is 74 dB, and the input referred current noise density is166.1 fA/Hz. This new method is suitable for biomedical applications such as electrocardiogram (ECG) signal acquisition.

Compact CMOS Analog Multiplier Free of Voltage Reference Generators

2020 ◽  
Vol 15 (3) ◽  
pp. 1-12
Author(s):  
Ana Isabela Araújo Cunha ◽  
Antonio José Sobrinho De Sousa ◽  
Edson Pinto Santana ◽  
Robson Nunes De Lima ◽  
Fabian Souza De Andrade ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Harmonic Distortion ◽  
Current Mode ◽  
Input Voltage ◽  
Voltage Reference ◽  
Analog Multiplier ◽  
Voltage Range ◽  
Voltage Variation ◽  
Static Power ◽  
Four Quadrant

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.

A 16.4 nW, Sub-1 V, Resistor-Less Voltage Reference with BJT Voltage Divider

2018 ◽  
Vol 27 (13) ◽  
pp. 1850206 ◽  
Author(s):  
Qingshan Yang ◽  
Peiqing Han ◽  
Niansong Mei ◽  
Zhaofeng Zhang
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Divider ◽  
Total Power ◽  
Cmos Process ◽  
Operating Voltage ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Total Power Consumption

A 16.4[Formula: see text]nW, sub-1[Formula: see text]V voltage reference for ultra-low power low voltage applications is proposed. This design reduces the operating voltage to 0.8[Formula: see text]V by a BJT voltage divider and decreases the silicon area considerably by eliminating resistors. The PTAT and CTAT are based on SCM structures and a scaled-down [Formula: see text], respectively, to improve the process insensitivity. This work is fabricated in 0.18[Formula: see text][Formula: see text]m CMOS process with a total area of 0.0033[Formula: see text]mm2. Measured results show that it works properly for supply voltage from 0.8[Formula: see text]V to 2[Formula: see text]V. The reference voltage is 467.2[Formula: see text]mV with standard deviation ([Formula: see text]) being 12.2 mV and measured TC at best is 38.7[Formula: see text]ppm/[Formula: see text]C ranging from [Formula: see text]C to 60[Formula: see text]C. The total power consumption is 16.4[Formula: see text]nW under the minimum supply voltage at 27[Formula: see text]C.

scholarly journals A Low Power Sigma-Delta Modulator with Hybrid Architecture

Sensors ◽  
2020 ◽  
Vol 20 (18) ◽  
pp. 5309
Author(s):  
Shengbiao An ◽  
Shuang Xia ◽  
Yue Ma ◽  
Arfan Ghani ◽  
Chan Hwang See ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Supply Voltage ◽  
Total Power ◽  
Cmos Process ◽  
Hybrid Architecture ◽  
Sigma Delta Modulator ◽  
Dynamic Comparator ◽  
Flash Adc ◽  
Total Power Consumption

Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption.

scholarly journals 60 GHz Front-End Components for Broadband Wireless Communication in 130 nm CMOS Technology

2016 ◽  
Vol 21 (1) ◽  
pp. 67-77
Author(s):  
Vasilis Kolios ◽  
Konstantinos Giannakidis ◽  
Grigorios Kalivas
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Spectral Space ◽  
60 Ghz ◽  
Front End ◽  
Total Power Consumption ◽  
5 Ghz

Abstract The over 5 GHz available spectral space allocated worldwide around the 60 GHz band, is very promising for very high data rate wireless short-range communications. In this article we present two key components for the 60 GHz front-end of a transceiver, in 130 nm RF CMOS technology: a single-balanced mixer with high Conversion Gain (CG), reduced Noise Figure (NF) and low power consumption, and an LC cross-coupled Voltage Controlled Oscillator (VCO) with very good linearity, with respect to Vctrl, and very low Phase Noise (PN). In both circuits, custom designed inductors and a balun structure for the mixer are employed, in order to enhance their performance. The VCO’s inductor achieves an inductance of 198 pH and a quality factor (Q) of 30, at 30 GHz. The balun shows less than 1o Phase Imbalance (PI) and less than 0.2 dB Amplitude Imbalance (AI), from 57 to 66 GHz. The mixer shows a CG greater than 15 dB and a NF lower than 12 dB. In addition, the VCO achieves a Phase Noise lower than -106 dBc/Hz at 1 MHz offset, and shows great linearity for the entire band. Both circuits are biased with a 1.2 V supply voltage and the total power consumption is about 10.6 mW for the mixer and 10.92 mW for the VCO.

scholarly journals Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

2018 ◽  
Vol 8 (6) ◽  
pp. 4922
Author(s):  
Anil Khatak ◽  
Manoj Kumar ◽  
Sanjeev Dhull
Keyword(s):  
Power Consumption ◽  
Leakage Current ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Power Reduction ◽  
Total Power ◽  
Low Power Consumption ◽  
Power Gating ◽  
Reduction Techniques ◽  
Total Power Consumption

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

HISTORY AND PROGRESS OF THE TOW–THOMAS BIQUADRATIC FILTER PART II: OTRA, CCII, AND DVCC REALIZATIONS

2008 ◽  
Vol 17 (05) ◽  
pp. 797-826 ◽  
Author(s):  
AHMED M. SOLIMAN
Keyword(s):  
Power Dissipation ◽  
Harmonic Distortion ◽  
Current Mode ◽  
Current Conveyor ◽  
Total Power ◽  
Feature Size ◽  
Biquadratic Filter ◽  
Simulation Results ◽  
Differential Voltage Current Conveyor ◽  
Very High

The realization of the Tow–Thomas (TT) circuit using the Operational Transresistance Amplifier (OTRA) is reviewed. The circuit employs two OTRA, and all passive elements are floating as the original Tow–Thomas circuit. The Current Conveyor (CCII) TT circuits are reviewed next. The progress in the realization of the TT circuit using CCII is demonstrated clearly by summarizing eight different circuits. One of the circuits has the advantage of very high input impedance using all grounded resistors and capacitors. The Differential Voltage Current Conveyor (DVCC) as the active building block in realizing the TT circuit is also considered. Finally, current mode TT circuits using balanced output CCII are summarized. Top Spice (level 49), simulation results using technology SCN 05 feature size 0.5 μm from MOSIS vendor: AGILENT are included to demonstrate the magnitude and phase frequency response of the TT circuits. Additional simulation results for the total power dissipation, total harmonic distortion, intermodulation IM3, input and output referred noise spectral densities are also included for comparison purposes.

scholarly journals An integrated 3.1–5.1 GHz pulse generator for ultra-wideband wireless localization systems

2006 ◽  
Vol 4 ◽  
pp. 247-250 ◽  
Author(s):  
X. Fan ◽  
G. Fischer ◽  
B. Dietrich
Keyword(s):  
Communication Systems ◽  
Pulse Shaping ◽  
Pulse Generator ◽  
Supply Voltage ◽  
Ultra Wideband ◽  
Center Frequency ◽  
Total Power ◽  
Gaussian Filter ◽  
Bicmos Technology ◽  
Total Power Consumption

Abstract. This paper presents an implementation of an integrated Ultra-wideband (UWB), Binary-Phase Shift Keying (BPSK) Gaussian modulated pulse generator. VCO, multiplier and passive Gaussian filter are the key components. The VCO provides the carrier frequency of 4.1 GHz, the LC Gaussian filter is responsible for the pulse shaping in the baseband. Multiplying the baseband pulse and the VCO frequency shifts the pulse to the desired center frequency. The generated Gaussian pulse ocupppies the frequency range from 3.1 to 5.1 GHz with the center frequency at 4.1 GHz. Simulations and measured results show that this spectrum fulfills the mask for indoor communication systems given by the FCC (Federal Communications Commission, 2002). The total power consumption is 55 mW using a supply voltage of 2.5 V. Circuits are realized using the IHP 0.25 μm SiGe:C BiCMOS technology.

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