MODELING AND ANALYSIS OF LOW POWER 10 T FULL ADDER WITH REDUCED GROUND BOUNCE NOISE

2014 ◽  
Vol 23 (01) ◽  
pp. 1450005 ◽  
Author(s):  
RAGHVENDRA SINGH ◽  
SHYAM AKASHE
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Performance ◽  
Digital Circuits ◽  
Arithmetic Operation ◽  
Full Adder ◽  
Leakage Power ◽  
Modeling And Analysis ◽  
Complex Arithmetic ◽  
Ground Bounce

In the design of high performance complex arithmetic logic circuits, ground bounce noise, leakage current and leakage power are important and challenging issues in nanometer down scaling. In this paper, the low power and reduced ground bounce noise using 10 transistor full adder has been proposed. Full adder is the most important basic building of digital circuits employing arithmetic operation. Adder circuit is widely used in many digital circuits not only for arithmetic operation but also for address generation in processors and microcontrollers. It is therefore necessary to make these systems more efficient so that they consume less power. Here, we use stacking power gating technique to evaluate leakage current, power and ground bounce noise. This paper describes reduction of leakage power and ground bounce noise from the 10 T full adder circuits to make it more reliable to be used to have low power and stable and errorless output. All the simulation in this paper has been carried out using cadence virtuoso at 45 nm technology at various voltages and various temperatures. By using this technique the leakage current reduction can be improved by 80% and leakage power to 70% as compared to conventional 10 T full adder. Ground bounce noise can be reduced to 60% as compared to the base full adder.

scholarly journals Forced stack sleep transistor (FORTRAN): A new leakage current reduction approach in CMOS based circuit designing

2021 ◽  
Vol 34 (2) ◽  
pp. 259-280
Author(s):  
Sankit Kassa ◽  
Neeraj Misra ◽  
Rajendra Nagaria
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Power Efficiency ◽  
High Performance ◽  
Low Voltage ◽  
Full Adder ◽  
Leakage Power ◽  
Modes Of Operation ◽  
Power Circuit ◽  
Current Reduction

Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4- bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.

Diode Based Trimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

2012 ◽  
Vol 548 ◽  
pp. 885-889 ◽  
Author(s):  
Manisha Pattanaik ◽  
Balwinder Raj ◽  
Shashikant Sharma ◽  
Anjan Kumar
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Performance ◽  
Room Temperature ◽  
Supply Voltage ◽  
Full Adder ◽  
Mode Analysis ◽  
Mode Transition ◽  
Additional Mode ◽  
Ground Bounce

In this paper a high performance diode based trimode Multi-Threshold CMOS (MTCMOS) technique is introduced which minimizes standby leakage current and provides a better way to control the ground bounce noise during sleep to active mode transition using one additional mode i.e. hold mode. Analysis of trimode MTCMOS technique using low power 16-bit full adder has been done for reduction of standby leakage current and ground bounce noise. Further, to evaluate the effectiveness of diode based trimode Multi-Threshold CMOS technique, simulation has been done on low power 16-bit full adder circuit with BPTM 90nm technology at room temperature with supply voltage of 1 V. Diode based trimode Multi-Threshold CMOS technique reduces ground bounce noise by 89.36% and standby leakage current by 19.24% as compared to the standard trimode MTCMOS technique.

scholarly journals OPTIMAL DESIGN FOR GROUND BOUNCE NOISE REDUCTION USING SLEEP TRANSISTOR

2012 ◽  
pp. 110-116
Author(s):  
P. Sreenivasulu ◽  
Vasavi Prasanthi Dasari
Keyword(s):  
Noise Immunity ◽  
Supply Voltage ◽  
Full Adder ◽  
Cmos Technology ◽  
Threshold Current ◽  
Active Power ◽  
Leakage Power ◽  
Analysis And Design ◽  
Complex Arithmetic ◽  
Ground Bounce

As technology scales into the nanometer regime ground bounce noise and noise immunity are becoming important metric of comparable importance to leakage current, active power, delay and area for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cells are proposed for mobile applications with low ground bounce noise and a novel technique has been introduced with improved staggered phase damping technique for further reduction in the peak of ground bounce noise. Noise immunity has been carefully considered since the significant threshold current of the low threshold voltage transition becomes more susceptible to noise. We introduced a new transistor resizing approach for 1bit full adder cells to determine the optimal sleep transistor size which reduce the leakage power and ground bounce noise. The simulation results depicts that the proposed design also leads to efficient 1bit full adder cells in terms of standby leakage power, active power, ground bounce noise and noise margin. We have performed simulations using Cadence Spectre 90nm standard CMOS technology at room temperature with supply voltage of 1V.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Speed ◽  
High Performance ◽  
Gate Oxide ◽  
Chemical Cleaning ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K ◽  
Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

DESIGN OF LOW POWER 14T FULL ADDER CELL USING DOUBLE GATE MOSFET WITH MTCMOS REDUCTION TECHNIQUE AT 45 NANOMETER TECHNOLOGY

2013 ◽  
Vol 12 (06) ◽  
pp. 1350042
Author(s):  
ANUJ KUMAR SHRIVASTAVA ◽  
SHYAM AKASHE
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Full Adder ◽  
Basic Block ◽  
Double Gate ◽  
Arithmetic Circuit ◽  
Double Gate Mosfet ◽  
Rf Devices ◽  
Power Application ◽  
Circuit Technique

Full adder is the basic block of arithmetic circuit found in microcontroller and microprocessor inside arithmetic and logic unit (ALU). Improving the performance of the adder is essential for upgrading the performance of digital electronics circuit where adder is employed. In this paper, a single bit full adder circuit has been designed with the help of double gate (MOSFET), the used parameters value has been varied significantly for improving the performance of full adder circuit. Double gate transistor circuit considers as a promising candidate for low power application domain as well as used in radio frequency (RF) devices. Multi-threshold CMOS (MTCMOS) is the most used circuit technique to reduce the leakage current in idle circuit. In this paper, different parameters are analyzed on MTCMOS Technique. MTCMOS technique achieves 99.6% reduction of leakage current, active power is reduced by 42.64% and delay is reduced by 71.9% as compared with conventional double gate 14T full adder. Simulation results of double gate full adder have been performed on cadence virtuoso tool with 45 nm technology.

Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell

2008 ◽  
Vol 3 (2) ◽  
Author(s):  
Keivan Navi ◽  
Omid Kavehei ◽  
Mahnoush Rouholamini ◽  
Amir Sahafi ◽  
Shima Mehrabi ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Full Adder
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