scholarly journals Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1256
Author(s):  
Seyedehsomayeh Hatefinasab ◽  
Noel Rodriguez ◽  
Antonio García ◽  
Encarnacion Castillo
Keyword(s):  
Standard Deviation ◽  
Power Consumption ◽  
Threshold Voltage ◽  
Low Cost ◽  
Process Variations ◽  
Cmos Technology ◽  
Soft Error ◽  
Single Event ◽  
Power Delay Product ◽  
The Impact

In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.

scholarly journals Static Switching Dynamic Buffer Circuit

2013 ◽  
Vol 2013 ◽  
pp. 1-11
Author(s):  
A. K. Pandey ◽  
R. A. Mishra ◽  
R. K. Nagaria
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Loading Condition ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Logic Function ◽  
Output Node ◽  
Switching Dynamic ◽  
Power Delay Product ◽  
Frequency Temperature

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.

Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations

2014 ◽  
Vol 24 (01) ◽  
pp. 1550007 ◽  
Author(s):  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Mahdi Fazeli
Keyword(s):  
Propagation Delay ◽  
Soft Error ◽  
The Other ◽  
Design Parameters ◽  
Single Event ◽  
Temperature Variations ◽  
Single Event Upsets ◽  
Radiation Hardened ◽  
Simulation Results ◽  
Power Delay Product

In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability of enduring single event multiple upsets (SEMUs). Our simulation results show that, both of our HRPU and HRUT latches have higher robustness against SEMUs as compared with other recently proposed radiation hardened latches. We have also explored the effects of process and temperature variations on different design parameters such as delay and power consumption of our proposed latches and other leading SEU tolerant latches. Our simulation results also show that, compared with the reference (unprotected) latch, our HRPU latch has 57% and 34% improvements in propagation delay and power delay product (PDP) respectively. In addition, process and temperature variations have least effects on HRPU in comparison with the other latches. Allowing little more delay, we designed HRUT latch that can filter single event transients (SETs). HRUT has been designed to be immune against SEUs, SEMUs and SETs with an acceptable overhead and sensitivity to process and temperature variations.

scholarly journals Impact of Fluid Flow on CMOS-MEMS Resonators Oriented to Gas Sensing

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4663
Author(s):  
Rafel Perello-Roig ◽  
Jaume Verd ◽  
Sebastià Bota ◽  
Jaume Segura
Keyword(s):  
Fluid Flow ◽  
Gas Sensing ◽  
Low Cost ◽  
Cmos Technology ◽  
Monolithically Integrated ◽  
Impact Reduction ◽  
Mems Resonators ◽  
Cmos Mems ◽  
Outstanding Result ◽  
The Impact

Based on experimental data, this paper thoroughly investigates the impact of a gas fluid flow on the behavior of a MEMS resonator specifically oriented to gas sensing. It is demonstrated that the gas stream action itself modifies the device resonance frequency in a way that depends on the resonator clamp shape with a corresponding non-negligible impact on the gravimetric sensor resolution. Results indicate that such an effect must be accounted when designing MEMS resonators with potential applications in the detection of volatile organic compounds (VOCs). In addition, the impact of thermal perturbations was also investigated. Two types of four-anchored CMOS-MEMS plate resonators were designed and fabricated: one with straight anchors, while the other was sustained through folded flexure clamps. The mechanical structures were monolithically integrated together with an embedded readout amplifier to operate as a self-sustained fully integrated oscillator on a commercial CMOS technology, featuring low-cost batch production and easy integration. The folded flexure anchor resonator provided a flow impact reduction of 5× compared to the straight anchor resonator, while the temperature sensitivity was enhanced to −115 ppm/°C, an outstanding result compared to the −2403 ppm/°C measured for the straight anchored structure.

scholarly journals HTNURL: Design of a High-Performance Low-Cost Triple-Node Upset Self-Recoverable Latch

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2457
Author(s):  
Hui Xu ◽  
Zehua Peng ◽  
Huaguo Liang ◽  
Zhengfeng Huang ◽  
Cong Sun ◽  
...  
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Feedback Loop ◽  
Low Cost ◽  
Low Power Consumption ◽  
Clock Gating ◽  
Single Node ◽  
Area Overhead ◽  
Power Delay Product ◽  
Reduced Power Consumption

A high-performance and low power consumption triple-node upset self-recoverable latch (HTNURL) is proposed. It can effectively tolerate single-node upset (SNU), double-node upset (DNU), and triple-node upset (TNU). This latch uses the C-element to construct a feedback loop, which reduces the delay and power consumption by fast path and clock gating techniques. Compared with the TNU-recoverable latches, HTNURL has a lower delay, reduced power consumption, and full self-recoverability. The delay, power consumption, area overhead, and area-power-delay product (APDP) of the HTNURL is reduced by 33.87%, 63.34%, 21.13%, and 81.71% on average.

scholarly journals Gate Sizing Methodology with a Novel Accurate Metric to Improve Circuit Timing Performance under Process Variations

Technologies ◽  
2020 ◽  
Vol 8 (2) ◽  
pp. 25 ◽  
Author(s):  
Zahira Perez-Rivera ◽  
Esteban Tlelo-Cuautle ◽  
Victor Champac
Keyword(s):  
Standard Deviation ◽  
Integrated Circuits ◽  
Computing Time ◽  
Process Variations ◽  
Path Selection ◽  
Economic Losses ◽  
Gate Sizing ◽  
Circuit Performance ◽  
Average Percentage ◽  
The Impact

The impact of process variations on circuit performance has become more critical with the technological scaling, and the increasing level of integration of integrated circuits. The degradation of the performance of the circuit means economic losses. In this paper, we propose an efficient statistical gate-sizing methodology for improving circuit speed in the presence of independent intra-die process variations. A path selection method, a heuristic, two coarse selection metrics, and one fine selection metric are part of the new proposed methodology. The fine metric includes essential concepts like the derivative of the standard deviation of delay, a path segment analysis, the criticality, the slack-time, and area. The proposed new methodology is applied to ISCAS Benchmark circuits. The average percentage of optimization in the delay is 12%, the average percentage of optimization in the delay standard deviation is 27.8%, the average percentage in the area increase is less than 5%, and computing time is up to ten times less than using analytical methods like Lagrange Multipliers.

scholarly journals Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Gagandeep Singh ◽  
Chakshu Goel
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Critical Path ◽  
Low Cost ◽  
Digital Systems ◽  
Xor Gate ◽  
Overall Performance ◽  
Carry Select Adder ◽  
Power Delay Product

In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA.

scholarly journals Design of a very low-power, low-cost 60 GHz receiver front-end implemented in 65 nm CMOS technology

2011 ◽  
Vol 3 (2) ◽  
pp. 131-138 ◽  
Author(s):  
Michael Kraemer ◽  
Daniela Dragomirescu ◽  
Robert Plana
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Low Cost ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
60 Ghz ◽  
Front End

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

Statistical Simulations on Perceptron-Based Adders

2011 ◽  
pp. 1474-1481
Author(s):  
Snorre Aunet ◽  
Hans Kristian Otnes Berge
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Reducing Power ◽  
Process Variations ◽  
Full Adder ◽  
Cmos Technology ◽  
Subthreshold Cmos ◽  
Order Of Magnitude ◽  
Supply Voltages ◽  
Circuit Technique

In this article we compare a number of full-adder (1- bit addition) cells regarding minimum supply voltage and yield, when taking statistical simulations into account. According to the ITRS Roadmap two of the most important challenges for future nanoelectronics design are reducing power consumption and increasing manufacturability (ITRS, 2005). We use subthreshold CMOS, which is regarded by many as the most promising ultra low power circuit technique. It is also shown that a minimum redundancyfactor as low as 2 is sufficient to make circuits maintain full functionality under the presence of defects. This is, to our knowledge, the lowest redundancy reported for comparable circuits, and builds on a method suggested a few years ago (Aunet & Hartmann, 2003). A standard Full-Adder (FA) and an FA based on perceptrons exploiting the “mirrored gate”, implemented in a standard 90 nm CMOS technology, are shown not to withstand statistical mismatch and process variations for supply voltages below 150 mV. Exploiting a redundancy scheme tolerating “open” faults, with gate-level redundancy and shorted outputs, shows that the same two FAs might produce adequate Sum and Carry outputs at the presence of a defect PMOS for supply voltages above 150 mV, for a redundancy factor of 2 (Aunet & Otnes Berge, 2007). Two additional perceptrons do not tolerate the process variations, according to simulations. Simulations suggest that the standard FA has the lowest power consumption. Power consumption varies more than an order of magnitude for all subthreshold FAs, due to the statistical variations

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