A Study on Theoretical Performance of Graphene FET using Analytical Approach with Reference to High Cutoff Frequency

2016 ◽  
Vol 15 (03) ◽  
pp. 1640001 ◽  
Author(s):  
Md. Fahim-Al-Fattah ◽  
Md. Tawabur Rahman ◽  
Md. Sherajul Islam ◽  
Ashraful G. Bhuiyan
Keyword(s):  
Field Effect ◽  
High Speed ◽  
Analytical Approach ◽  
Cutoff Frequency ◽  
Channel Length ◽  
Significant Shift ◽  
Field Effect Devices ◽  
High Transconductance ◽  
Graphene Fet ◽  
Theoretical Performance

This paper presents a detailed study of theoretical performance of graphene field effect transistor (GFET) using analytical approach. GFET shows promising performance in terms of faster saturation as well as extremely high cutoff frequency (3.9[Formula: see text]THz). A significant shift of the Dirac point as well as an asymmetrical ambipolar behavior is observed on the transfer characteristics. Similarly, an approximate symmetrical capacitance–voltage (C–V) characteristics is obtained where it has guaranteed the consistency because it shows a significant saturation both in the accumulation and inversion region. In addition, a high transconductance of 6800[Formula: see text]uS at small channel length (20[Formula: see text]nm) along with high cutoff frequency (3.9[Formula: see text]THz) has been observed which demands for high speed field effect devices.

An analytical approach to calculate effective channel length in graphene nanoribbon field effect transistors

2013 ◽  
Vol 53 (4) ◽  
pp. 540-543 ◽  
Author(s):  
M. Ghadiry ◽  
M. Nadi ◽  
M. Bahadorian ◽  
Asrulnizam ABD Manaf ◽  
H. Karimi ◽  
...  
Keyword(s):  
Field Effect ◽  
Analytical Approach ◽  
Field Effect Transistors ◽  
Channel Length ◽  
Graphene Nanoribbon ◽  
Effective Channel

SLD-MOSCNT: A new MOSCNT with step–linear doping profile in the source and drain regions

2017 ◽  
Vol 31 (01) ◽  
pp. 1650242 ◽  
Author(s):  
Behrooz Abdi Tahne ◽  
Ali Naderi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Cutoff Frequency ◽  
Basic Structure ◽  
Channel Length ◽  
Doping Profile ◽  
Horizontal Distance ◽  
Short Channel ◽  
Channel Effects ◽  
Channel Lengths

In this paper, a new structure, step–linear doping MOSCNT (SLD-MOSCNT), is proposed to improve the performance of basic MOSCNTs. The basic structure suffers from band to band tunneling (BTBT). We show that using SLD profile for source and drain regions increases the horizontal distance between valence and conduction bands at gate to source/drain junction which reduces BTBT probability. SLD performance is compared with other similar structures which have recently been proposed to reduce BTBT such as MOSCNT with lightly-doped drain and source (LDDS), and with double-light doping in source and drain regions (DLD). The obtained results using a nonequilibrium Green’s function (NEGF) method show that the SLD-MOSCNT has the lowest leakage current, power consumption and delay time, and the highest current ratio and voltage gain. The ambipolar conduction in the proposed structure is very low and can be neglected. In addition, these structures can improve short-channel effects. Also, the investigation of cutoff frequency of the different structures shows that the SLD has the highest cutoff frequency. Device performance has been investigated for gate length from 8 to 20 nm which demonstrates all discussions regarding the superiority of the proposed structure are also valid for different channel lengths. This improvement is more significant especially for channel length less than 12 nm. Therefore, the SLD can be considered as a candidate to be used in the applications with high speed and low power consumption.

scholarly journals Gallium Arsenide as a Competitor to Silicon for High-speed Amplification and Switching

1982 ◽  
Vol 35 (6) ◽  
pp. 749
Author(s):  
PH Ladbrooke ◽  
DR Debuf ◽  
K Nanayakkara ◽  
DR Wilkins
Keyword(s):  
Field Effect ◽  
High Speed ◽  
Field Effect Transistors ◽  
Electrical Characteristics ◽  
Electrical Behaviour ◽  
Technological Factors ◽  
Ballistic Electron ◽  
Ballistic Electron Transport ◽  
Field Effect Devices ◽  
Transport Effects

A review is given of the physical and technological factors which affect the electrical behaviour of field-effect devices for high-speed applications. Ballistic electron transport is shown to lead to an electron transit time under the gate electrode which is shorter in GaAs than in Si field-effect transistors (FETs), providing a possible basis for exploitation of transport effects in high-speed devices. Some electrical characteristics of practical Si and GaAs field-effect structures are presented.

Dc and Microwave Characteristics of High Transconductance AlGaN/GaN Heterostructure Field Effect Transistors on Sic Substrates

1997 ◽  
Vol 482 ◽  
Author(s):  
Q. Chen ◽  
J. W. Yang ◽  
M. A. Khan ◽  
A. T. Ping ◽  
I. Adesida
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Cutoff Frequency ◽  
Channel Current ◽  
Heterostructure Field Effect Transistors ◽  
High Power Operation ◽  
Drain Bias ◽  
Gan Heterostructure ◽  
High Transconductance ◽  
P Type

AbstractHigh quality AJGaN/GaN heterostructures have been successfully deposited on both nand p-type SiC substrates. Heterostructure field effect transistors fabricated using these layers exhibited high channel current density (1.71 A/mm), well behaved pinch-off characteristics, and excellent extrinsic transconductance (Gm = 229 mS/mm). There is negligible channel current degradation up to a source to drain bias of 20 V as opposed to devices grown on sapphire substrates. The 0.25 μm gate-length devices fabricated on the heterostructures grown on p-type SiC has allowed us to extract a cutoff frequency of 53 GHz. The cutoff frequency showed little deterioration with increasing drain bias voltage. These results demonstrate for the first time the high frequency and high power operation potential of the heterostructure field effect transistors based on AlGaN grown on SiC.

Active Field Effect Capacitive Sensors for High-throughput, Label-free Nucleic Acid Analysis

2008 ◽  
Vol 1139 ◽  
Author(s):  
Manu Sebastian Mannoor ◽  
Teena James ◽  
Dentcho V. Ivanov ◽  
Bill Braunlin ◽  
Les Beadling
Keyword(s):  
Nucleic Acid ◽  
High Throughput ◽  
Field Effect ◽  
Oxide Semiconductor ◽  
Significant Shift ◽  
Capacitive Sensors ◽  
Label Free ◽  
Dna Arrays ◽  
Field Effect Devices ◽  
Nucleic Acid Analysis

AbstractWe report a highly selective technique for the rapid and label-free analysis of nucleic acid sample using Metal Oxide Semiconductor (MOS) capacitive sensors. The binding of charged macromolecules such as DNA on the surface of these Field Effect Devices modifies the charge distribution in the Semiconductor (Si) region of the sensor. These changes are manifested as a significant shift in the Capacitance-Voltage (C-V) characteristics measured across the device. The speed and selectivity of the detection process is enhanced by the use of external electric field of controlled intensity. This simple and high-throughput sensing technique holds promises for the future electronic DNA arrays and Lab-on-a chip devices

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

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