SLD-MOSCNT: A new MOSCNT with step–linear doping profile in the source and drain regions

In this paper, a new structure, step–linear doping MOSCNT (SLD-MOSCNT), is proposed to improve the performance of basic MOSCNTs. The basic structure suffers from band to band tunneling (BTBT). We show that using SLD profile for source and drain regions increases the horizontal distance between valence and conduction bands at gate to source/drain junction which reduces BTBT probability. SLD performance is compared with other similar structures which have recently been proposed to reduce BTBT such as MOSCNT with lightly-doped drain and source (LDDS), and with double-light doping in source and drain regions (DLD). The obtained results using a nonequilibrium Green’s function (NEGF) method show that the SLD-MOSCNT has the lowest leakage current, power consumption and delay time, and the highest current ratio and voltage gain. The ambipolar conduction in the proposed structure is very low and can be neglected. In addition, these structures can improve short-channel effects. Also, the investigation of cutoff frequency of the different structures shows that the SLD has the highest cutoff frequency. Device performance has been investigated for gate length from 8 to 20 nm which demonstrates all discussions regarding the superiority of the proposed structure are also valid for different channel lengths. This improvement is more significant especially for channel length less than 12 nm. Therefore, the SLD can be considered as a candidate to be used in the applications with high speed and low power consumption.

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Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

Circulation in Computer Science ◽

10.22632/ccs-2017-251-50 ◽

2017 ◽

Vol 2 (2) ◽

pp. 15-19 ◽

Cited By ~ 3

Author(s):

Md. Saud Al Faisal ◽

Md. Rokib Hasan ◽

Marwan Hossain ◽

Mohammad Saiful Islam

Keyword(s):

High Speed ◽

Field Effect Transistors ◽

Cmos Technology ◽

Channel Length ◽

Capacitive Coupling ◽

Oxide Semiconductor ◽

Double Gate ◽

Short Channel ◽

Channel Effects ◽

Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

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Design and Characterization of the Next Generation Nanowire Amplifiers

VLSI Design ◽

10.1155/2008/190315 ◽

2008 ◽

Vol 2008 ◽

pp. 1-5

Author(s):

Sotoudeh Hamedi-Hagh ◽

Ahmet Bindal

Keyword(s):

High Speed ◽

Field Effect Transistors ◽

Channel Length ◽

Next Generation ◽

Short Channel ◽

Surrounding Gate ◽

Channel Effects ◽

Gate Control ◽

Voltage Swing

Vertical nanowire surrounding gate field effect transistors (SGFETs) provide full gate control over the channel to eliminate short-channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10 nm channel length and a 2 nm channel radius. The amplifier dissipates 5 μW power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V, and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd- and 3rd-order harmonic distortions of the amplifier are −40 dBm and −52 dBm, respectively, and the 3rd-order intermodulation is −24 dBm for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high-speed analog and VLSI technologies.

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Short-channel and high-mobility p- and n-type organic single-crystal transistors with air-gap structures

MRS Proceedings ◽

10.1557/opl.2012.261 ◽

2012 ◽

Vol 1402 ◽

Author(s):

M. Uno ◽

T. Uemura ◽

K. Miwa ◽

A. Facchetti ◽

J. Takeya

Keyword(s):

Single Crystal ◽

High Speed ◽

Carrier Mobility ◽

Field Effect Transistors ◽

High Mobility ◽

Channel Length ◽

Air Gap ◽

Short Channel ◽

Glass Substrates ◽

Channel Lengths

ABSTRACTIn an effort to realize high-speed organic logic components, p- and n-type single-crystal organic field-effect transistors (SC-OFETs) were fabricated using air-gap structures with channel lengths as short as several μm. High carrier mobility of about 10 cm2/Vs is demonstrated in rubrene SC-OFETs even with the short channel length of 6 μm, using Si-based microstructures. The contact resistance is estimated to be 450 Ohm cm, which is only 5% of the total channel resistance between source and drain electrodes. Performances of n-type air-gap devices based on PDIF-CN2 are also demonstrated exhibiting electron transport with the carrier mobility of about 2 cm2/Vs. Furthermore, micron-scale air-gap structures are fabricated using insulating materials on glass substrates to reduce parasitic gate capacitance. The cut-off frequency of this rubrene air-gap device is measured to be as high as 8 MHz with applied drain voltage VD of 15 V. These techniques are promising to be applicable to next-generation organic high-speed logic circuits.

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Influence of Channel Length and High-K Oxide Thickness on Subthreshold DC Performance of Graded Channel and Gate Stack DG-MOSFETs

NANO ◽

10.1142/s1793292016501010 ◽

2016 ◽

Vol 11 (09) ◽

pp. 1650101 ◽

Cited By ~ 9

Author(s):

Sarosij Adak ◽

Sanjit Kumar Swain ◽

Arka Dutta ◽

Hafizur Rahaman ◽

Chandan Kumar Sarkar

Keyword(s):

High Speed ◽

Oxide Thickness ◽

Channel Length ◽

Gate Stack ◽

Short Channel ◽

Power Circuit ◽

Novel Device ◽

High K ◽

Channel Effects ◽

High Speed Switching

Comparative assessment of graded channel gate stack (GCGS) DG MOSFET structure is done by using two-dimensional (2D) Sentrausu TCAD simulator for different high K oxide thickness. This novel device includes gate stack (GS) engineering (high K) and nonuniformly channel engineering (GC) to suppress the short channel effects and improve the device performance. This novel device can be a better alternative for the future high speed switching and low power circuit applications. It has the advantage of improved breakdown voltage, reduced leakage current, low output conductance and reduced bipolar parasitic effects. The given device must be properly investigated with respect to the variation of different high K oxide thickness on different parameters such as drain induced barrier lowering (DIBL), subthreshold slope (SS), [Formula: see text]/[Formula: see text], [Formula: see text] roll off before fabrication to have better reliability. The 2D Sentrausu TCAD simulator using drift-diffusion model was used to simulate the developed structure and good agreement is obtained with respect to already published result in the sub-threshold regime. The result indicates that there is a need to be optimize the DC parameters for specific circuit applications.

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Review of CMOS Amplifiers for High Frequency Applications

International Journal of Engineering and Advanced Technology - Regular Issue ◽

10.35940/ijeat.b2101.1210220 ◽

2020 ◽

Vol 10 (2) ◽

pp. 175-180

Keyword(s):

Power Consumption ◽

High Frequency ◽

High Speed ◽

Short Channel Effects ◽

Performance Parameters ◽

Short Channel ◽

Channel Effects ◽

High Bandwidth ◽

Cmos Amplifier ◽

User Friendly

The headway in electronics technology proffers user-friendly devices. The characteristics such as high integration, low power consumption, good noise immunity are the significant benefits that CMOS offer, paying many challenges simultaneously with it. The short channel effects and presence of parasitic which prevent speed pose questions on the performance parameters. A great sort of works has done by many groups in the design of the CMOS amplifier for high-frequency applications to discuss the parameters such as power consumption, high bandwidth, high speed and linearity trade-off to obtain an optimized output. A lot of amplifier topologies are experimented and discussed in the literature with its design and simulation. In this paper, the various efforts associated with CMOS amplifier circuit for high-frequency applications are studying extensively.

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Hot Carrier Effects in Deep Submicron Nmosfets

MRS Proceedings ◽

10.1557/proc-428-385 ◽

1996 ◽

Vol 428 ◽

Author(s):

Abhijit Phanse ◽

Samar Saha

Keyword(s):

Electric Fields ◽

Channel Length ◽

Deep Submicron ◽

Short Channel ◽

Hot Carrier ◽

Velocity Saturation ◽

Substrate Current ◽

Hot Carrier Effects ◽

Saturation Effects ◽

Channel Lengths

AbstractThis paper addresses hot-carrier related reliability issues in deep submicron silicon nMOSFET devices. In order to monitor the hot-carrier induced device degradation, the substrate current was measured for devices with varying channel lengths (20 um - 0.24 um) under various biasing conditions. Deep submicron devices experience velocity saturation of channel carriers due to extremely high lateral electric fields. To evaluate the effects of velocity saturation in the channel, the pinch-off length in the channel was extracted for all the devices of the target technology. It was observed that for very short channel devices, carriers in most of the channel experience velocity saturation and almost the entire channel gets pinched off. It is shown in this paper that for very short channel devices, the pinch-off length in the channel is limited by the effective channel length, and that velocity saturation effects are critical to the transport of channel carriers.

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Scaling down of organic thin film transistors: short channel effects and channel length-dependent field effect mobility

Journal of Materials Science ◽

10.1007/s10853-008-3047-6 ◽

2009 ◽

Vol 44 (1) ◽

pp. 280-284 ◽

Cited By ~ 21

Author(s):

Yi Chen ◽

Ishiang Shih

Keyword(s):

Field Effect ◽

Channel Length ◽

Organic Thin Film Transistors ◽

Short Channel Effects ◽

Organic Thin Film ◽

Field Effect Mobility ◽

Short Channel ◽

Channel Effects ◽

Scaling Down ◽

Dependent Field

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The Effect of Doping on Different FET Structures: MOSFET, TFET and FinFET

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.f4051.049620 ◽

2020 ◽

Vol 9 (6) ◽

pp. 972-979

Keyword(s):

Drain Current ◽

Channel Length ◽

Short Channel Effects ◽

Poor Control ◽

Short Channel ◽

Circuit Performance ◽

The Past ◽

Channel Effects ◽

Circuit Density ◽

Effect Of Doping

MOSFET have been scaled down over the past few years in order to give rise to high circuit density and increase the speed of circuit. But scaling of MOSFET leads to issues such as poor control gate over the current which depends on gate voltage. Many short channel effects (SCE) influence the circuit performance and leads to the indeterminist response of drain current. These effects can be decreased by gate excitation or by using multiple gates and by offering better control gate the device parameters. In Single gate MOSFET, gate electric field decreases but multigate MOSFET or FinFET provides better control over drain current. In this paper, different FET structures such as MOSFET, TFET and FINFET are designed at 22nm channel length and effect of doping had been evaluated and studied. To evaluate the performance donor concentration is kept constant and acceptor concentration is varied.

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