Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

For improving retention characteristics in the NOR flash array, aluminum oxide (Al2O3, alumina) is utilized and incorporated as a tunneling layer. The proposed tunneling layers consist of SiO2/Al2O3/SiO2, which take advantage of higher permittivity and higher bandgap of Al2O3 compared to SiO2 and silicon nitride (Si3N4). By adopting the proposed tunneling layers in the NOR flash array, the threshold voltage window after 10 years from programming and erasing (P/E) was improved from 0.57 V to 4.57 V. In order to validate our proposed device structure, it is compared to another stacked-engineered structure with SiO2/Si3N4/SiO2 tunneling layers through technology computer-aided design (TCAD) simulation. In addition, to verify that our proposed structure is suitable for NOR flash array, disturbance issues are also carefully investigated. As a result, it has been demonstrated that the proposed structure can be successfully applied in NOR flash memory with significant retention improvement. Consequently, the possibility of utilizing HfO2 as a charge-trapping layer in NOR flash application is opened.

Download Full-text

Physics-Based TCAD Simulation and Calibration of 600 V GaN/AlGaN/GaN Device Characteristics and Analysis of Interface Traps

Micromachines ◽

10.3390/mi12070751 ◽

2021 ◽

Vol 12 (7) ◽

pp. 751

Author(s):

Yu-Lin Song ◽

Manoj Kumar Reddy ◽

Luh-Maan Chang ◽

Gene Sheu

Keyword(s):

Conduction Band ◽

Computer Aided Design ◽

Measurement Data ◽

High Electron Mobility Transistor ◽

High Electron ◽

Device Structure ◽

Gan Hemt ◽

Fixed Charges ◽

Vertical Electric Field ◽

Aided Design

This study proposes an analysis of the physics-based TCAD (Technology Computer-Aided Design) simulation procedure for GaN/AlGaN/GaN HEMT (High Electron Mobility Transistor) device structures grown on Si (111) substrate which is calibrated against measurement data. The presence of traps and activation energies in the device structure will impact the performance of a device, the source of traps and position of traps in the device remains as a complex exercise until today. The key parameters for the precise tuning of threshold voltage (Vth) in GaN transistors are the control of the positive fixed charges −5 × 1012 cm−2, donor-like traps −3 × 1013 cm−2 at the nitride/GaN interfaces, the energy of the donor-like traps 1.42 eV below the conduction band and the acceptor traps activation energy in the AlGaN layer and buffer regions with 0.59 eV below the conduction band. Hence in this paper, the sensitivity of the trap mechanisms in GaN/AlGaN/GaN HEMT transistors, understanding the absolute vertical electric field distribution, electron density and the physical characteristics of the device has been investigated and the results are in good agreement with GaN experimental data.

Download Full-text

Flash memory based on solution processed hafnium dioxide charge trapping layer

Journal of Materials Chemistry C ◽

10.1039/c4tc00010b ◽

2014 ◽

Vol 2 (21) ◽

pp. 4233-4238 ◽

Cited By ~ 9

Author(s):

Jiaqing Zhuang ◽

Su-Ting Han ◽

Ye Zhou ◽

V. A. L. Roy

Keyword(s):

Flash Memory ◽

Sol Gel ◽

Charge Trapping ◽

Hafnium Dioxide ◽

Solution Processed ◽

Gel Technique ◽

A Charge

Hafnium dioxide (HfO2) film prepared by the sol–gel technique has been used as a charge trapping layer in organic flash memory.

Download Full-text

Polysilicon–Oxide–Nitride–Oxide–Silicon-Type Flash Memory Using an Y[sub 2]O[sub 3] Film as a Charge Trapping Layer

Electrochemical and Solid-State Letters ◽

10.1149/1.2919136 ◽

2008 ◽

Vol 11 (7) ◽

pp. G37 ◽

Cited By ~ 1

Author(s):

Tung-Ming Pan ◽

Wen-Wei Yeh

Keyword(s):

Flash Memory ◽

Charge Trapping ◽

A Charge ◽

Nitride Oxide

Download Full-text

A New Read Scheme for Alleviating Cell-to-Cell Interference in Scaled-Down 3D NAND Flash Memory

Electronics ◽

10.3390/electronics9111775 ◽

2020 ◽

Vol 9 (11) ◽

pp. 1775

Author(s):

Jae-Min Sim ◽

Myounggon Kang ◽

Yun-Heub Song

Keyword(s):

Electric Field ◽

Flash Memory ◽

Computer Aided Design ◽

Fundamental Problem ◽

Adjacent Cell ◽

Nand Flash ◽

Nand Flash Memory ◽

Fundamental Cause ◽

Tcad Simulation ◽

Aided Design

In this paper, we investigated the cell-to-cell interference in scaled-down 3D NAND flash memory by using a Technology Computer-Aided Design (TCAD) simulation. The fundamental cause of cell-to-cell interference is that the electric field crowding point is changed by the programmed adjacent cell so that the electric field is not sufficiently directed to the channel surface. Therefore, the channel concentration of the selected cell is changed, leading to a Vth shift. Furthermore, this phenomenon occurs more severely when the selected cell is in an erased state rather than in a programmed state. In addition, it was confirmed that the cell-to-cell interference by the programmed WLn+1 is more severe than that of WLn−1 due to the degradation of the effective mobility effect. To solve this fundamental problem, a new read scheme is proposed. Through TCAD simulation, the cell-to-cell interference was alleviated with a bias having a ΔV of 1.5 V from Vread through an optimization process to have appropriate bias conditions in three ways that are suitable for each pattern. As a result, this scheme narrowed the Vth shift of 67.5% for erased cells and narrowed the Vth shift of 70% for programmed cells. The proposed scheme is one way to solve the cell-to-cell interference that may occur as the cell-to-cell distance decreases for a high stacked 3D NAND structure.

Download Full-text

A Nonvolatile InGaZnO Charge-Trapping-Engineered Flash Memory With Good Retention Characteristics

IEEE Electron Device Letters ◽

10.1109/led.2009.2037986 ◽

2010 ◽

Vol 31 (3) ◽

pp. 201-203 ◽

Cited By ~ 32

Author(s):

Nai-Chao Su ◽

Shui Jinn Wang ◽

A. Chin

Keyword(s):

Flash Memory ◽

Charge Trapping ◽

Retention Characteristics ◽

Good Retention

Download Full-text

Chemical-Vapor-Deposited Graphene as Charge Storage Layer in Flash Memory Device

Journal of Nanomaterials ◽

10.1155/2016/6751497 ◽

2016 ◽

Vol 2016 ◽

pp. 1-6 ◽

Cited By ~ 2

Author(s):

W. J. Liu ◽

L. Chen ◽

P. Zhou ◽

Q. Q. Sun ◽

H. L. Lu ◽

...

Keyword(s):

Flash Memory ◽

Room Temperature ◽

Metal Layer ◽

Chemical Vapor ◽

Charge Trapping ◽

Memory Device ◽

Water Molecules ◽

Oh Groups ◽

Chemical Vapor Deposited ◽

A Charge

We demonstrated a flash memory device with chemical-vapor-deposited graphene as a charge trapping layer. It was found that the average RMS roughness of block oxide on graphene storage layer can be significantly reduced from 5.9 nm to 0.5 nm by inserting a seed metal layer, which was verified by AFM measurements. The memory window is 5.6 V for a dual sweep of ±12 V at room temperature. Moreover, a reduced hysteresis at the low temperature was observed, indicative of water molecules or −OH groups between graphene and dielectric playing an important role in memory windows.

Download Full-text

3D AND-Type Stacked Array for Neuromorphic Systems

Micromachines ◽

10.3390/mi11090829 ◽

2020 ◽

Vol 11 (9) ◽

pp. 829

Author(s):

Taejin Jang ◽

Suhyeon Kim ◽

Jeesoo Chang ◽

Kyung Kyu Min ◽

Sungmin Hwang ◽

...

Keyword(s):

Flash Memory ◽

Computer Aided Design ◽

Power Level ◽

Matrix Multiplication ◽

Simple Program ◽

Neuromorphic Systems ◽

Tcad Simulation ◽

Cell Variation ◽

Aided Design ◽

Implantation Method

NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.

Download Full-text

A Semi-Floating Gate Memory Based on SOI Substrate by TCAD Simulation

Electronics ◽

10.3390/electronics8101198 ◽

2019 ◽

Vol 8 (10) ◽

pp. 1198

Author(s):

Han Li ◽

Chen Wang ◽

Lin Chen ◽

Hao Zhu ◽

Qingqing Sun

Keyword(s):

Computer Aided Design ◽

Random Access ◽

Floating Gate ◽

Silicon On Insulator ◽

Semiconductor Electronic ◽

Floating Gate Memory ◽

Retention Characteristics ◽

Tcad Simulation ◽

Aided Design ◽

Physical Challenges

Over the past decade, the dimensional scaling of semiconductor electronic devices has been facing fundamental and physical challenges, and there is currently an urgent need to increase the ability of dynamic random-access memory (DRAM). A semi-floating gate (SFG) transistor has been proposed as a capacitor-less memory with faster speed and higher density as compared with the conventional one-transistor one-capacitor (1T1C) DRAM technology. The integration of SFG-based memory on the silicon-on-insulator (SOI) substrate has been demonstrated in this work by using the Sentaurus Technology Computer-Aided Design (TCAD) simulation. An enhancement in retention characteristics, anti-disturbance ability, and fast writing capability, have been illustrated. The device exhibits a low operation voltage, a large threshold voltage window of ~3 V, and an ultra-fast writing of 4 ns. In addition, the SOI-based memory has shown a much-improved anti-irradiation capability compared to the devices based on bulk silicon, which makes it much more attractive in broader applications.

Download Full-text