scholarly journals Analysis of CNT Bundle and Its Comparison with Copper Interconnect for CMOS and CNFET Drivers

2009 ◽  
Vol 2009 ◽  
pp. 1-6 ◽  
Author(s):  
Abdul Kadir Kureshi ◽  
Mohd. Hasan
Keyword(s):  
Integrated Circuits ◽  
Energy Efficient ◽  
High Speed ◽  
Comprehensive Evaluation ◽  
High Resistivity ◽  
Cmos Process ◽  
Process Technology ◽  
Delay Reduction ◽  
Effect Transistor ◽  
Cu Interconnect

In nanoscale regime as the CMOS process technology continues to scale, the standard copper (Cu) interconnect will become a major hurdle for onchip communication due to high resistivity and electromigration. This paper presents the comprehensive evaluation of mixed CNT bundle interconnects and investigates their prospects as a low power high-speed interconnect for future nanoscale-integrated circuits. The performance of mixed CNT bundle interconnect is examined with carbon nanotube field effect transistor (CNFET) as a driver and compared with the traditional interconnect, that is, CMOS driver on Cu interconnect. All HSPICE simulations are carried out at operating frequency of 1 GHz and it is found that mixed CNT bundle interconnects with CNFET as the driver can potentially provide a substantial delay reduction over traditional interconnects implemented at 32 nm process technology. Similarly, the CNFET driver with mixed CNT bundle as interconnect is more energy efficient than the traditional interconnect at all supply voltages (VDD) from 0.9 V to 0.3 V.

scholarly journals Performance Optimization and Comparison of CNT Interconnect with Copper at VDSM Technology

2013 ◽  
Vol 6 (2) ◽  
pp. 826-834
Author(s):  
Kureshi Abdul Kadir ◽  
Mohd Hasan
Keyword(s):  
Carbon Nanotube ◽  
Performance Optimization ◽  
Energy Efficient ◽  
Deep Submicron ◽  
Copper Interconnects ◽  
Cmos Process ◽  
Process Technology ◽  
Technology Node ◽  
Global Interconnects ◽  
Cu Interconnect

As the CMOS process technology continues to scale, standard copper (Cu) interconnect will become a major hurdle for the best performance at very deep submicron (VDSM) technology node. The carbon nanotube (CNT) bundles have potential to provide an attractive solution for the higher resistivity and electromigration problems faced by traditional copper interconnects in VDSM technology node. This paper presents important guidelines to minimize the resistance, capacitance and inductance of a mixed CNT bundle interconnect for achieving best performance. The performance of mixed CNT bundle and copper is then compared at local and global interconnects level at 22nm technology node. HSPICE simulations carried out using Berkeley predictive technology model (BPTM) at an operating frequency of 1GHz, shows that for interconnect length of 1000um, the mixed CNT and optimized CNT (CNT_Opt) bundles are 1.98X and 2.20X faster, 74% and 84% more energy efficient respectively than the Copper interconnects.

scholarly journals A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2260
Author(s):  
Khuram Shehzad ◽  
Deeksha Verma ◽  
Danial Khan ◽  
Qurat Ul Ain ◽  
Muhammad Basim ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Intelligent Transportation System ◽  
Cmos Process ◽  
Process Technology ◽  
Back Issue ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

DESIGN DIFFERENT TOPOLOGY FOR REDUCTION OF LOW POWER 2:1 MULTIPLEXER USING FINFET IN NANOMETER TECHNOLOGIES

2013 ◽  
Vol 12 (04) ◽  
pp. 1350026
Author(s):  
KHUSHBOO MISHRA ◽  
SHYAM AKASHE
Keyword(s):  
Field Effect Transistor ◽  
Access Time ◽  
Cmos Process ◽  
Process Technology ◽  
Gate Control ◽  
Operating Current ◽  
Pass Transistor ◽  
Effect Transistor ◽  
Power Leakage ◽  
Current Operating

The intention of this paper is to reduce power and area of 2:1 multiplexer (MUX) while maintaining the competitive performance. The various configurations are designed using different topology of 2:1 MUX such as CMOS-based MUX, transmission gate and pass transistor using fin-shaped field effect transistor (FINFET). The mobility was enhanced in devices with taller fins due to increase tensile stress. In DG, FINFET can be efficiently used to develop performance and reduce power consumption. In noncritical paths self-determining gate control can be used to join together parallel transistors. We have estimated the optimum power, optimum current, leakage power, leakage current, operating power, operating current and delay in voltage supply 0.7 V at different temperature such as 10°C, 27°C and 50°C, respectively. A 20 ns access time and frequency 0.5 GHz provide 45 nm CMOS process technology with 0.7 V power supply is employed to carry out different topology of 2:1 MUX using FINFET.

Device Applications of Low-Temperature-Grown GaAs

1991 ◽  
Vol 241 ◽  
Author(s):  
Frank W. Smith
Keyword(s):  
Low Temperature ◽  
Integrated Circuits ◽  
High Speed ◽  
Gate Insulator ◽  
Metal Insulator ◽  
Unique Material ◽  
Device Applications ◽  
Effect Transistor ◽  
Commercial Applications ◽  
Microwave Switch

ABSTRACTLow-temperature-grown (LTG) GaAs is a unique material that has been used in a variety of device applications to achieve record performance. LTG GaAs used as a buffer layer eliminates sidegating and backgating and in GaAs integrated circuits. Record output power density (1.57 W/mm) and superior microwave-switch performance were demonstrated when LTG GaAs was used at a gate insulator in a metal-insulator-semiconductor field-effect transistor. High-speed (0.5 ps) and high-voltage (1 kV) LTG GaAs photoconductive switches have also been demonstrated. Using the same material, researchers have demonstrated highresponsivity (0.1 A/W), wide-bandwidth (∼ 375 GHz) LTG GaAs photodetectors. Devices incorporating LTG GaAs are currently being optimized for systems applications. LTG GaAs technology can enhance system performance and enable new systems for military and commercial applications in the areas of radar, communications, instrumentation, and highspeed computing.

scholarly journals Implementation of Pruned Backpropagation Neural Network Based on Photonic Integrated Circuits

Photonics ◽  
2021 ◽  
Vol 8 (9) ◽  
pp. 363
Author(s):  
Qi Zhang ◽  
Zhuangzhuang Xing ◽  
Duan Huang
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Integrated Circuits ◽  
Energy Efficient ◽  
High Speed ◽  
Large Scale ◽  
Matrix Operation ◽  
Optical Neural Networks ◽  
Optical Neural Network ◽  
Random Initialization

We demonstrate a pruned high-speed and energy-efficient optical backpropagation (BP) neural network. The micro-ring resonator (MRR) banks, as the core of the weight matrix operation, are used for large-scale weighted summation. We find that tuning a pruned MRR weight banks model gives an equivalent performance in training with the model of random initialization. Results show that the overall accuracy of the optical neural network on the MNIST dataset is 93.49% after pruning six-layer MRR weight banks on the condition of low insertion loss. This work is scalable to much more complex networks, such as convolutional neural networks and recurrent neural networks, and provides a potential guide for truly large-scale optical neural networks.

High-Speed CMOS Frequency Dividers with Symmetric In-Phase and Quadrature Waveforms

2016 ◽  
Vol 25 (10) ◽  
pp. 1630006
Author(s):  
Sungkyung Park ◽  
Chester Sungchung Park
Keyword(s):  
Duty Cycle ◽  
High Speed ◽  
Logic Gate ◽  
Memory Systems ◽  
Data Converters ◽  
Frequency Divider ◽  
Cmos Process ◽  
Process Technology ◽  
Dynamic Memory ◽  
Frequency Dividers

Frequency dividers are used in frequency synthesizers to generate specific frequencies or clock (CK) waveforms. As consequences of their operating principles, frequency dividers often produce output waveforms that exhibit duty cycles other than 50%. However, some circuits and systems, including dynamic memory systems and data converters, which accommodate frequency divider outputs, may need symmetric or 50%-duty-cycle clock waveforms to optimize timing margins or to obtain sufficient timing reliability. In this review paper, design principles and methods are studied to produce symmetric waveforms for the in-phase (I) and quadrature (Q) outputs of high-speed CMOS frequency dividers with design considerations from the logic gate level down to the transistor level in terms of speed, reliability, noise, and latency. A compact and robust multi-gigahertz frequency divider with moduli 12, 14, and 16 to provide I and Q outputs with 50% duty cycle is proposed and designed using a 90-nm digital CMOS process technology with 1.2-V supply.

A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology

2017 ◽  
Vol 26 (11) ◽  
pp. 1750182
Author(s):  
Indrit Myderrizi ◽  
Ali Zeki
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Output Voltage ◽  
High Speed ◽  
Pulse Signal ◽  
Propagation Delay ◽  
Cmos Process ◽  
Down Low ◽  
Voltage Swing ◽  
Output Voltage Swing

With the increase in demand for high-speed and low-power integrated circuits as technology scales down, low-swing signaling circuit techniques are critical for providing high-speed low-power communications. However, existing low-swing circuits comprise complex designs, power issues (static and dynamic), output voltage swing restrictions or nonadjustable voltage swing levels, leading to lower operation speeds and even larger area footprints. In this paper, a tunable swing-reduced driver (SRD) circuit featuring the mentioned design challenges is presented. The SRD enables low-swing signals with fully controllable output voltage swing that is useful to reduce the power dissipation and delay in the signaling paths. Implemented in UMC 0.13-[Formula: see text][Formula: see text]m multi-threshold CMOS process, the SRD achieves 26 ps propagation delay at 200[Formula: see text]mV output swing for a pulse signal input at 1[Formula: see text]GHz. Post-layout simulations of the proposed SRD and a DAC application circuit, incorporating the SRD, operating at 1[Formula: see text]GHz, validate the design.

Gallium arsenide electronics in the marketplace

1992 ◽  
Vol 70 (10-11) ◽  
pp. 943-945
Author(s):  
Paul R. Jay.
Keyword(s):  
Gallium Arsenide ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Large Scale ◽  
Low Cost ◽  
Logic Gates ◽  
Process Technology ◽  
Maximum Benefit ◽  
Technological Developments

The last few years have seen a significant emergence of real product applications using gallium arsenide metal semi-conductor field effect transistor technology. These applications range from large volume consumer markets based on small low-cost GaAs integrated circuits to high-end supercomputer products using very large scale integrated GaAs chips containing up to 50 000 logic gates. This situation represents substantial advances in many areas: materials technology, device and integrated circuit process technology, packaging and high speed testing, as well as appropriate system design to obtain maximum benefit from the GaAs technology. This paper reviews some recent commercial successes, and considers commonalities existing between them in the context of recent technological developments.

SINGLE-EVENT EFFECTS IN III-V SEMICONDUCTOR ELECTRONICS

2004 ◽  
Vol 14 (02) ◽  
pp. 311-325 ◽  
Author(s):  
DALE McMORROW ◽  
JOSEPH S. MELINGER ◽  
ALVIN R. KNUDSON
Keyword(s):  
Energy Transfer ◽  
Integrated Circuits ◽  
Field Effect ◽  
High Speed ◽  
Field Effect Transistor ◽  
Single Event Upset ◽  
Single Event ◽  
Single Event Effects ◽  
Semiconductor Electronics ◽  
Effect Transistor

Single-event effects are a serious concern for high-speed III-V semiconductor devices operating in radiation-intense environments. GaAs integrated circuits (ICs) based on field effect transistor technology exhibit single-event upset sensitivity to protons and very low linear energy transfer (LET) particles. The current understanding of single-event effects in III-V circuits and devices, and approaches for mitigating their impact, are discussed.

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