scholarly journals Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Gagandeep Singh ◽  
Chakshu Goel
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Critical Path ◽  
Low Cost ◽  
Digital Systems ◽  
Xor Gate ◽  
Overall Performance ◽  
Carry Select Adder ◽  
Power Delay Product

In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA.

Novel Architecture for Low-Power CNTFET-Based Compressors

2019 ◽  
Vol 28 (12) ◽  
pp. 1950207 ◽  
Author(s):  
Morteza Dadashi Gavaber ◽  
Mehrdad Poorhosseini ◽  
Saadat Pourmozafari
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Field Effect Transistors ◽  
Critical Path ◽  
Building Blocks ◽  
Cmos Circuits ◽  
Xor Gate ◽  
Speed Reduction ◽  
Different Types ◽  
Power Delay Product

Carbon nanotube field-effect transistors (CNTFETs) are excellent candidates for the replacement of traditional CMOS circuits. One of the most important modules in many arithmetic circuits is multiplier. Sometimes multipliers may occupy more area as well as consume high power which may cause speed reduction in the critical path. Compressors are important building blocks which are used in most multipliers. In this paper, a low-power architecture is proposed which can be used in compressor designs. The proposed architecture uses a low-power three-input XOR gate to reduce area, delay and power consumption. In order to evaluate the delay and power consumption of circuits, we have used four different types of compressors (3–2, 4–2, 5–2 and 7–2). These four designs were simulated using HSPICE simulation tool with 32-nm CMOS model based on 1-V and 1-GHz frequency operator. The results indicate that the proposed compressor architectures have less power–delay product (PDP) and power consumption in comparison with the existing proposed compressors.

scholarly journals IMPLEMENTATION OF HIGH SPEED-LOW POWER TRUNCATION ERROR TOLERANT ADDER

2015 ◽  
pp. 239-244
Author(s):  
SYAM KUMAR NAGENDLA ◽  
K. MIRANJI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Processing System ◽  
Digital Signal ◽  
Signal Processing System ◽  
Speed Performance ◽  
Power Delay Product ◽  
Dsp Systems

Now a Days in modern VLSI technology different kinds of errors are invitable. A new type of adder i.e. error tolerant adder(ETA) is proposed to tolerate those errors and to attain low power consumption and high speed performance in DSP systems. In conventional adder circuit, delay is mainly certified to the carry propagation chain along the critical path, from the LSB to MSB. If the carry propagation can be eliminated by the technique proposed in this paper, a great improvement in speed performance and power consumption is achieved. By operating shifting and addition in parallel, the error tolerant adder tree compensates for the truncation errors. To prove the feasibility of the ETA, normal addition operation present in the DFT or DCT algorithm is replaced by the proposed addition arithmetic and the experimental results are shown. In this paper we propose error tolerant Adder (ETA). In the view of DSP applications the ETA is able to case the strict restriction on accuracy, speed performance and power consumption when compared to the conventional Adders, the proposed one provides 76% improvement in power-delay product such a ETA plays a key role in digital signal processing system that can tolerate certain amount of errors.

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

scholarly journals Integration of highly anisotropic multiferroic BaTiO3–Fe nanocomposite thin films on Si towards device applications

2020 ◽  
Vol 2 (9) ◽  
pp. 4172-4178
Author(s):  
Matias Kalaswad ◽  
Bruce Zhang ◽  
Xuejing Wang ◽  
Han Wang ◽  
Xingyao Gao ◽  
...  
Keyword(s):  
Thin Films ◽  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Low Cost ◽  
Low Power Consumption ◽  
Silicon Substrates ◽  
Critical Step ◽  
Nanocomposite Thin Films ◽  
Device Applications

Integration of highly anisotropic multiferroic thin films on silicon substrates is a critical step towards low-cost devices, especially high-speed and low-power consumption memories.

Semi-Physical Simulation System for FMCW Radar

2011 ◽  
Vol 135-136 ◽  
pp. 886-892
Author(s):  
Wen Hui Chen ◽  
Xin Xi Meng ◽  
Xiao Min Liu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Physical Simulation ◽  
Continuous Wave ◽  
Low Cost ◽  
Simulation System ◽  
Radar Signal ◽  
Low Power Consumption ◽  
Fmcw Radar ◽  
Data Process

In order to process and analyze the signal of frequency modulated continuous wave (FMCW) radar, a radar semi-physical simulation(RSPS) system based on STM32F103VE6 chip is designed in this paper. By designing the hardware and software of system, the RSPS system can process the radar signal, detect the target, verify the data process algorithm and display the result on TFT-LCD screen. In addition, the collected data can be uploaded to PC by RS-232 interfaces which improves the reliability, stability and practicability of system. The waveform and spectrum maps are utilized to show the feasibility of RSPS system in analysing FMCW radar signal. Experimental results show that this system has many advantages, such as multifunction, low power consumption and low cost.

Bluetooth Hands Free System for Fixed Telephone Research

2012 ◽  
Vol 198-199 ◽  
pp. 1603-1608
Author(s):  
Qing Hua Shang ◽  
Ping Liu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Mobile Phones ◽  
Daily Life ◽  
Low Cost ◽  
Low Power Consumption ◽  
Wireless Technology ◽  
Free System ◽  
Wireless Technologies ◽  
The Stability

Wireless technology has walked into the People's Daily life, Bluetooth technology comes to the fore in so many wireless technologies with its low power consumption, low cost and other characteristics. Bluetooth technology is used widely, we can see it in mobile phones or in our cars, it seems that Bluetooth technology has penetrated into every aspect of our lives. Even so, the combination of Bluetooth technology and fixed telephone still has a very big development space. If the stability of the fixed telephone combined with the flexible of Bluetooth technology, it will give the life of people a lot of convenience. This paper will introduces the Bluetooth hands free system for fixed telephone, it is such a product that it will make Bluetooth technology and common fixed phone combined, and make it a reality that people can use common Bluetooth headset to answer or call a fixed telephone.

Tunable Low Power UWB Transmitter for WBAN Application

2015 ◽  
Vol 24 (03) ◽  
pp. 1550040 ◽  
Author(s):  
V. Vinod Kumar ◽  
M. Meenakshi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Efficiency ◽  
Delay Line ◽  
Data Transfer ◽  
Low Cost ◽  
Wireless Body Area Network ◽  
Superior Performance ◽  
Area Network ◽  
Coverage Area

This paper presents the design and simulation results for a Federal Communication Committee (FCC) complaint current starved delay line based Ultra Wide Band (UWB) Gaussian pulse transmitter, which is designed for operating in the 3.1–10.6 GHz range. The wavelet is a mono cycle Gaussian impulse wave, which is practically well suited for low cost, low power, low data rate wireless data transfer such as in wireless body area network (WBAN) applications. The transmitter operating frequency and bandwidth (BW) is controlled using a dc voltage provided at the input stage of a voltage controlled delay line (VCDL) and this aspect can be exploited for increasing the communication coverage area without compromising on the power consumption. A Gaussian wave shaping is performed for FCC compliance and the simulation has been carried out with 130 nm technology. The simulation of our design suggests an average dynamic power consumption of 1.11 mw for an energy efficiency of 14.2 pJ/pulse. The proposed IR-UWB transmitter design though a bit inferior in terms of the power efficiency, can claim superior performance with respect to tuning the BW, which is very relevant in a cognitive wireless networking scenario with other interfering signals.

scholarly journals HTNURL: Design of a High-Performance Low-Cost Triple-Node Upset Self-Recoverable Latch

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2457
Author(s):  
Hui Xu ◽  
Zehua Peng ◽  
Huaguo Liang ◽  
Zhengfeng Huang ◽  
Cong Sun ◽  
...  
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Feedback Loop ◽  
Low Cost ◽  
Low Power Consumption ◽  
Clock Gating ◽  
Single Node ◽  
Area Overhead ◽  
Power Delay Product ◽  
Reduced Power Consumption

A high-performance and low power consumption triple-node upset self-recoverable latch (HTNURL) is proposed. It can effectively tolerate single-node upset (SNU), double-node upset (DNU), and triple-node upset (TNU). This latch uses the C-element to construct a feedback loop, which reduces the delay and power consumption by fast path and clock gating techniques. Compared with the TNU-recoverable latches, HTNURL has a lower delay, reduced power consumption, and full self-recoverability. The delay, power consumption, area overhead, and area-power-delay product (APDP) of the HTNURL is reduced by 33.87%, 63.34%, 21.13%, and 81.71% on average.

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