scholarly journals From FPGA to Support Cloud to Cloud of FPGA: State of the Art

2019 ◽  
Vol 2019 ◽  
pp. 1-17 ◽  
Author(s):  
Rym Skhiri ◽  
Virginie Fresse ◽  
Jean Paul Jamont ◽  
Benoit Suffran ◽  
Jihene Malek
Keyword(s):  
Cloud Computing ◽  
Power Consumption ◽  
Field Programmable Gate Array ◽  
State Of The Art ◽  
Low Power Consumption ◽  
Domain Specific ◽  
Field Programmable ◽  
Major Trend ◽  
Computationally Expensive ◽  
Significant Attention

Field Programmable Gate Array (FPGA) draws a significant attention from both industry and academia by accelerating computationally expensive applications and achieving low power consumption. FPGAs are interesting due to the flexibility and reconfigurabiltiy of their device. Cloud computing becomes a major trend towards infrastructure and computing resources dematerialization. It provides “unlimited” storage capacities and a large number of data and applications that make collaboration easier between multiple (not domain specific) designers. Many papers in the literature have surveyed Cloud and FPGA separately and, more precisely, their services and challenges. The acceleration of applications by FPGA and the unlimited capacities of the cloud are expected to be more and more pervasive. As more and more FPGA are being deployed in traditional cloud, it is appropriate to clarify what is the cloud FPGA and which drawbacks of using FPGA in local are resolved. We present a survey of the cloud FPGA works that have been proposed to exploit the advantages of using FPGA in the cloud. We classify these studies in three services to highlight their benefits and limitations. This survey aims at motivating further researches in cloud FPGA.

scholarly journals High speed multi-channel data acquisition technique for efficient hardware utilization using quad data rate approach

2018 ◽  
Vol 7 (4) ◽  
pp. 2569
Author(s):  
Priyanka Chauhan ◽  
Dippal Israni ◽  
Karan Jasani ◽  
Ashwin Makwana
Keyword(s):  
Power Consumption ◽  
Data Acquisition ◽  
Resource Utilization ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
State Of The Art ◽  
Data Rate ◽  
Field Programmable ◽  
Sensor Signals ◽  
Acquisition Technique

Data acquisition is the most demanding application for the acquisition and monitoring of various sensor signals. The data received are processed in real-time environment. This paper proposes a novel Data Acquisition (DAQ) technique for better resource utilization with less power consumption. Present work has designed and compared advanced Quad Data Rate (QDR) technique with traditional Dual Data Rate (DDR) technique in terms of resource utilization and power consumption of Field Programmable Gate Array (FPGA) hardware. Xilinx ISE is used to verify results of FPGA resource utilization by QDR with state of the art DDR approach. The paper ratiocinates that QDR technique outperforms traditional DDR technique in terms of FPGA resource utilization.  

scholarly journals VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

2021 ◽  
Vol 14 (1) ◽  
pp. 22-31
Author(s):  
Kommalapati Monica ◽  
◽  
Dereddy Anuradha ◽  
Syed Rasheed ◽  
Barnala Shereesha ◽  
...  
Keyword(s):  
Power Consumption ◽  
Field Programmable Gate Array ◽  
Finite Impulse Response ◽  
Research Work ◽  
Industrial Applications ◽  
Booth Multiplier ◽  
Wallace Tree ◽  
Look Up Table ◽  
Field Programmable ◽  
Wallace Tree Multiplier

Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

Challenges in 3D Inspection of Micro Bumps Used in 3D Packaging

2012 ◽  
Vol 2012 (1) ◽  
pp. 000542-000547 ◽  
Author(s):  
Reza Asgari
Keyword(s):  
Power Consumption ◽  
Wafer Bonding ◽  
Field Programmable Gate Array ◽  
Laser Triangulation ◽  
3D Measurement ◽  
Lower Power ◽  
Small Pitch ◽  
Field Programmable ◽  
3D Packaging ◽  
2D And 3D

2.5D/3D devices are the next major packaging technologies, driven by the need for more functionality, lower power consumption and smaller footprint. Many device manufacturers are devoting capital to develop their own processes and some are already shipping devices such as FPGA (Field Programmable Gate Array) on interposers. 3D packages often require hundreds of thousands of I/O per die. Micro Pillar bumps and C4 bumps are the main bump geometries used in 3D packages as their small pitch and size allow the required number of I/Os. Inspecting these bumps throughout the process is critical because failure after chip to chip or chip to wafer bonding is very costly. This paper describes the use of a camera and laser triangulation to provide complete 2D and 3D measurement and inspection capability.

scholarly journals Design of Energy Efficient Control Unit and Implementation on High Performance FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 23-26
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Control Unit ◽  
Input Output ◽  
Green Communication ◽  
Power Efficient ◽  
Efficient Control ◽  
Field Programmable

With the crisis of power across the globe, green communication and power-efficient devices are getting more and more attention. This work emphasis about the implementation of Control Unit (CU) circuit on FPGA kit. In this project, power consumption of CU circuit is analyzed by changing the different Input/Output (I/O) standards of FPGA. This project is implemented on Xilinx 14.1 tool and the power consumption on CU is calculated with X Power Analyzer tool on 28-Nano-Meter (nm) Artix-7 Field Programmable Gate Array (FPGA). Out of different I/O standards, CU circuit is most power efficient with LVCMOS I/O standard on Artix-7 FPGA

Design and implementation of power and area optimized AES architecture on FPGA for IoT application

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Rajasekar P. ◽  
Mangalam H.
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Data Storage ◽  
Resource Sharing ◽  
Low Power Consumption ◽  
Multiplicative Inverse ◽  
Content Type ◽  
Field Programmable ◽  
Pipe Line ◽  
Affine Transforms

Purpose The growing trends in the usage of hand held devices necessitate the need to design them with low power consumption and less area design. Besides, information security is gaining enormous importance in information transmission and data storage technology. In addition, today’s technology world is connected, communicated and controlled via the Internet of Things (IoT). In many applications, the most standard and widely used cryptography algorithm for providing security is Advanced Encryption Standard (AES). This paper aims to design an efficient model of AES cryptography for low power and less area. Design/methodology/approach First, the main issues related to less area and low power consumption in the AES encryption core are addressed. To implement optimized AES core, the authors proposed optimized multiplicative inverse, affine transforms and Xtime multipliers functions, which are the core function of AES’s core. In addition, to achieve the high throughput, it uses the multistage pipeline and resource reuse architectures for SBox and Mixcolumn of AES. Findings The results of optimized AES architecture have revealed that the multistage pipe line and resource sharing are optimal design model in Field Programmable Gate Array (FPGA) implementation. It could provide high security with low power and area for IoT and wireless sensors networks. Originality/value This proposed optimized modified architecture has been implemented in FPGA to calculate the power, area and delay parameters. This multistage pipeline and resource sharing have promised to minimize the area and power.

scholarly journals Bubble-Proof Algorithm for Wave Union TDCs

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 30
Author(s):  
Paweł Kwiatkowski ◽  
Dominik Sondej ◽  
Ryszard Szplet
Keyword(s):  
Field Programmable Gate Array ◽  
Hardware Implementation ◽  
State Of The Art ◽  
Single Shot ◽  
Output Data ◽  
Data Encoding ◽  
Field Programmable ◽  
Output Code ◽  
Efficient Data ◽  
Fpga Chip

Nowadays state-of-the-art time-to-digital converters (TDCs) are commonly implemented in field-programmable gate array (FPGA) devices using different variations of the wave union method. To take full advantage of this method many design challenges need to be overcome, one of which is an efficient data encoding. In this work, we describe in detail an effective algorithm to decode raw output data from a newly designed multisampling wave union TDC. The algorithm is able to correct bubble errors and detect any number of transitions, which occur in the wave union TDC output code. This allows us to reach a mean resolution as high as 0.39 ps and a single shot precision of 2.33 ps in the Xilinx Kintex-7 FPGA chip. The presented algorithm can be used for any kind of wave union TDCs and is intended for partial hardware implementation.

scholarly journals Hardware-Based Activation Function-Core for Neural Network Implementations

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 14
Author(s):  
Griselda González-Díaz_Conti ◽  
Javier Vázquez-Castillo ◽  
Omar Longoria-Gandara ◽  
Alejandro Castillo-Atoche ◽  
Roberto Carrasco-Alvarez ◽  
...  
Keyword(s):  
Power Consumption ◽  
State Of The Art ◽  
Activation Function ◽  
Reconfigurable Architecture ◽  
Low Power Consumption ◽  
Piecewise Polynomial ◽  
Activation Functions ◽  
Medical Systems ◽  
Piecewise Polynomial Approximation ◽  
The Internet Of Things

Today, embedded systems (ES) tend towards miniaturization and the carrying out of complex tasks in applications such as the Internet of Things, medical systems, telecommunications, among others. Currently, ES structures based on artificial intelligence using hardware neural networks (HNNs) are becoming more common. In the design of HNN, the activation function (AF) requires special attention due to its impact on the HNN performance. Therefore, implementing activation functions (AFs) with good performance, low power consumption, and reduced hardware resources is critical for HNNs. In light of this, this paper presents a hardware-based activation function-core (AFC) to implement an HNN. In addition, this work shows a design framework for the AFC that applies a piecewise polynomial approximation (PPA) technique. The designed AFC has a reconfigurable architecture with a wordlength-efficient decoder, i.e., reduced hardware resources are used to satisfy the desired accuracy. Experimental results show a better performance of the proposed AFC in terms of hardware resources and power consumption when it is compared with state of the art implementations. Finally, two case studies were implemented to corroborate the AFC performance in widely used ANN applications.

scholarly journals A Study on the Energetic Viability of Single Board Computers for Cloud Computing Scenarios

2017 ◽  
Author(s):  
Pedro Verdugo ◽  
Joaquín Salvachúa ◽  
Gabriel Huecas
Keyword(s):  
Cloud Computing ◽  
Power Consumption ◽  
Energy Efficient ◽  
Low Cost ◽  
Power Saving ◽  
Low Power Consumption ◽  
Full System ◽  
Processing Power ◽  
Relevant Case

The following document explores the viability of the usage of consumer-grade, ARM-based single board computers as a power saving alternative to the traditional monolithic x64-full-server based approach.By taking advantage of several capabilities provided by such devices, such as low cost, low power consumption and low on-time, the authors finally propose a scalable, energy-efficient, ARM-based cloud infrastructure.To that end, we start analyzing the current offerings in terms of capabilities, net cost, processing power and power consumption, comparing them with the relevant server-oriented offerings.We subsequently explore the adequacy of several metrics to model on-budget raw data processing, considering full-system wattage under nominal usage conditions.The low initial investment and long-term affordability of this approach results in quite a relevant case of application to Edge Cloud computing scenarios.

scholarly journals Survey: Internet of Thing Using FPGA

2017 ◽  
Vol 13 (1) ◽  
pp. 38-45 ◽  
Author(s):  
Noor Jumaa
Keyword(s):  
Field Programmable Gate Array ◽  
Information Society ◽  
Smart Devices ◽  
Low Power Consumption ◽  
Single Chip ◽  
Field Programmable ◽  
Iot Platforms ◽  
Iot Devices ◽  
On Chip ◽  
Internet Of Thing

Everything in its way to be computerized and most of the objects are coming to be smart in present days. Modern Internet of Thing (IoT) allows these objects to be on the network by using IoT platforms. IoT is a smart information society that consists of smart devices; these devices can communicate with each other without human's intervention. IoT systems require flexible platforms. Through the use of Field Programmable Gate Array (FPGA), IoT devices can interface with the outside world easily with low power consumption, low latency, and best determinism. FPGAs provide System on Chip (SoC) technique due to FPGAs scalability which enables the designer to implement and integrate large number of hardware clocks at single chip. FPGA can be deemed as a special purpose reprogrammable processor since it can process signals at its input pins, manipulate them, and give off signals on the output pins. In this paper, using FPGA for IoT is the limelight.

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