scholarly journals A New Type of Tri-Input TFET with T-Shaped Channel Structure Exhibiting Three-Input Majority Logic Behavior

2021 ◽  
Vol 2021 ◽  
pp. 1-11
Author(s):  
Ye Hao ◽  
Jiang Zhidi ◽  
Hu Jianping

In this paper, we propose a new type of tri-input tunneling field-effect transistor (Ti-TFET) that can compactly realize the “Majority-Not” logic function with a single transistor. It features an ingenious T-shaped channel and three independent-biasing gates deposited and patterned on its left, right, and upper sides, which greatly enhance the electrostatic control ability between any two gates of all the three gates on the device channel and thus increase its turn-on current. The total current density and energy band distribution in different biasing conditions are analyzed in detail by TCAD simulations. The turn-on current, leakage current, and ratio of turn-on/off current are optimized by choosing appropriate work function and body thickness. TCAD simulation results verify the expected characteristics of the proposed Ti-TFETs in different working states. Ti-TFETs can flexibly be used to implement a logic circuit with a compact style and thus reduce the number of transistors and stack height of the circuits. It provides a new technique to reduce the chip area and power consumption by saving the number of transistors.

2018 ◽  
Vol 32 (34n36) ◽  
pp. 1840072
Author(s):  
Yibo Jiang ◽  
Hui Bi ◽  
Hui Li

The bulk fin field-effect transistor (FinFET) has been the primary semiconductor technology in nanotechnology. To protect low supply voltage circuits based on FinFET, trigger voltage [Formula: see text] of the silicon controlled rectifier (SCR) which acts as electrostatic discharge (ESD) protection device should be lowered further. In this paper, in order to lower the [Formula: see text] an extra implant technique is proposed to form bridging well low trigger voltage FinFET SCR (FinFET BRLVTSCR). The experiments demonstrate that the trigger voltage can be lowered effectively. Moreover, the TCAD simulations bring an in-depth physical understanding of ESD current conduction and failure mechanism during ESD protection. Finally, the turn-on characteristic demonstrates proposed novel SCRs are fast and effective under TLP and very fast TLP (VFTLP) stress.


2015 ◽  
Vol 36 (4) ◽  
pp. 309-311 ◽  
Author(s):  
Yoshiyuki Kobayashi ◽  
Daisuke Matsubayashi ◽  
Suguru Hondo ◽  
Tsutomu Yamamoto ◽  
Yutaka Okazaki ◽  
...  

Electronics ◽  
2018 ◽  
Vol 7 (8) ◽  
pp. 126 ◽  
Author(s):  
Lina Wang ◽  
Junyi Yang ◽  
Haobo Ma ◽  
Zeyuan Wang ◽  
Kabir Olanrewaju ◽  
...  

Silicon Carbide (SiC)-based Bi-Directional Switches (BDS) have great potential in the construction of several power electronic circuits including multi-level converters, solid-state breakers, matrix converters, HERIC (high efficient and reliable inverter concept) photovoltaic grid-connected inverters and so on. In this paper, two issues with the application of SiC-based BDSs, namely, unwanted turn-on and parasitic oscillation, are deeply investigated. To eliminate unwanted turn-on, it is proposed to add a capacitor (CX) paralleled at the signal input port of the driver IC (integrated circuit) and the capacitance range of CX is also analytically derived to guide the selection of CX. To mitigate parasitic oscillation, a combinational method, which combines a snubber capacitor (CJ) paralleled with the JFET (Junction Field Effect Transistor) and a ferrite ring connected in series with the power line, is proposed. It is verified that the use of CJ mainly improves the turn-off transient and the use of a ferrite ring damps the current oscillation during the turn-on transient significantly. The effects of the proposed methods have been demonstrated by theoretical analysis and verified by experimental results.


Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2619
Author(s):  
Jongwoon Yoon ◽  
Kwangsoo Kim

In this study, a novel MOS-channel diode embedded in a SiC superjunction MOSFET (MCD SJ-MOSFET) is proposed and analyzed by means of numerical TCAD simulations. Owing to the electric field shielding effect of the P+ body and the P-pillar, the channel diode oxide thickness (tco) of MCD can be set to very thin while achieving a low maximum oxide electric field (EMOX) under 3 MV/cm. Therefore, the turn-on voltage (VF) of the proposed structure was 1.43 V, deactivating the parasitic PIN body diode. Compared with the SJ-MOSFET, the reverse recovery time (trr) and the reverse recovery charge (Qrr) were improved by 43% and 59%, respectively. Although there is a slight increase in specific on-resistance (RON), the MCD SJ-MOSFET shows very low input capacitance (CISS) and gate to drain capacitance (CGD) due to the reduced active gate. Therefore, significantly improved figures of merit RON × CGD by a factor of 4.3 are achieved compared to SJ-MOSFET. As a result, the proposed structure reduced the switching time as well as the switching energy loss (ESW). Moreover, electro-thermal simulation results show that the MCD SJ-MOSFET has a short circuit withstand time (tSC) more than twice that of the SJ-MOSFET at various DC bus voltages (400 and 600 V).


Nanomaterials ◽  
2020 ◽  
Vol 10 (10) ◽  
pp. 1931
Author(s):  
Minh Nhat Dang ◽  
Minh Dang Nguyen ◽  
Nguyen Khac Hiep ◽  
Phan Ngoc Hong ◽  
In Hyung Baek ◽  
...  

We herein present an alternative geometry of nanostructured carbon cathode capable of obtaining a low turn-on field, and both stable and high current densities. This cathode geometry consisted of a micro-hollow array on planar carbon nanostructures engineered by femtosecond laser. The micro-hollow geometry provides a larger edge area for achieving a lower turn-on field of 0.70 V/µm, a sustainable current of approximately 2 mA (about 112 mA/cm2) at an applied field of less than 2 V/µm. The electric field in the vicinity of the hollow array (rim edge) is enhanced due to the edge effect, that is key to improving field emission performance. The edge effect of the micro-hollow cathode is confirmed by numerical calculation. This new type of nanostructured carbon cathode geometry can be promisingly applied for high intensity and compact electron sources.


2020 ◽  
Vol 24 (05n07) ◽  
pp. 929-937
Author(s):  
Ewa Jaworska ◽  
Fabrizio Caroleo ◽  
Corrado Di Natale ◽  
Krzysztof Maksymiuk ◽  
Roberto Paolesse ◽  
...  

We present here a new type of fluoride ion optode, constituted by a highly lipophilic PVDF porous membrane modified with a liquid receptor layer containing the emission-active Si corrole F[Formula: see text] selective ionophore. For the optimized composition of the receptor layer, in acidic solutions an increase of Si-corrole emission was observed by increasing fluoride ion concentration, a behavior different from most porphyrinoid-based optical sensors. An observed linear dependence of the Si corrole emission intensity (read at 635 nm) was within the range 10[Formula: see text] to 10[Formula: see text] M of fluoride ions.


2012 ◽  
Vol 220-223 ◽  
pp. 2360-2363
Author(s):  
Yan Jun Sun ◽  
Chang Ming Liu ◽  
Hai Yu Li ◽  
Zhe Yuan

Multivariate quadratic based public-key cryptography called MQ problem which based on calculation of a secure cryptography of multivariate equations and MQ cryptography security is based on the difficulty of the solution of multivariate equations. But computer and mathematician scientists put a lot of effort and a long time to research MQ cryptography and they have proved that MQ cryptography is NP complete problem. Therefore, before the P problem Equal to the NP problem we do not figure out selected multivariate equations by random in polynomial time. So we can use this feature to construct the relative safety method of the public key encryption. A new type of public-key cryptosystem has been brought up in this paper that one-way shell core function which has such advantages as more security and flexibility, and provides a more inclusive public-key cryptosystem.


2016 ◽  
Vol 108 (3) ◽  
pp. 033101 ◽  
Author(s):  
Ž. Gačević ◽  
D. López-Romero ◽  
T. Juan Mangas ◽  
E. Calleja

Author(s):  
B. HARIKRISHNA ◽  
DR.S. RAVI

In commercial architectures, the routing consumes most of the chip area, and is responsible for most of the circuit delay. In this paper a new technique of reconfiguring FPGA circuits is proposed. The proposed technique uses BLRB approach for reconfiguring the FPGA. By this approach the routing path is less and the overall delay required to recover from fault is very less. Whenever any fault occurs the spare is selected in such way that whichever spare is nearer is chosen for reconfiguration. By selecting the nearest spare the routing path is decreased. In this method multiple faults are reconfigured at a time and the reconfigured bits are generated.


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