scholarly journals A Novel MOS-Channel Diode Embedded in a SiC Superjunction MOSFET for Enhanced Switching Performance and Superior Short Circuit Ruggedness

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2619
Author(s):  
Jongwoon Yoon ◽  
Kwangsoo Kim

In this study, a novel MOS-channel diode embedded in a SiC superjunction MOSFET (MCD SJ-MOSFET) is proposed and analyzed by means of numerical TCAD simulations. Owing to the electric field shielding effect of the P+ body and the P-pillar, the channel diode oxide thickness (tco) of MCD can be set to very thin while achieving a low maximum oxide electric field (EMOX) under 3 MV/cm. Therefore, the turn-on voltage (VF) of the proposed structure was 1.43 V, deactivating the parasitic PIN body diode. Compared with the SJ-MOSFET, the reverse recovery time (trr) and the reverse recovery charge (Qrr) were improved by 43% and 59%, respectively. Although there is a slight increase in specific on-resistance (RON), the MCD SJ-MOSFET shows very low input capacitance (CISS) and gate to drain capacitance (CGD) due to the reduced active gate. Therefore, significantly improved figures of merit RON × CGD by a factor of 4.3 are achieved compared to SJ-MOSFET. As a result, the proposed structure reduced the switching time as well as the switching energy loss (ESW). Moreover, electro-thermal simulation results show that the MCD SJ-MOSFET has a short circuit withstand time (tSC) more than twice that of the SJ-MOSFET at various DC bus voltages (400 and 600 V).

2019 ◽  
Vol 963 ◽  
pp. 797-800 ◽  
Author(s):  
Ajit Kanale ◽  
Ki Jeong Han ◽  
B. Jayant Baliga ◽  
Subhashish Bhattacharya

The high-temperature switching performance of a 1.2kV SiC JBSFET is compared with a 1.2kV SiC MOSFET using a clamped inductive load switching circuit representing typical H-bridge inverters. The switching losses of the SiC MOSFET are also evaluated with a SiC JBS Diode connected antiparallel to it. Measurements are made with different high-side and low-side device options across a range of case temperatures. The JBSFET is observed to display a reduction in peak turn-on current – up to 18.9% at 150°C and a significantly lesser turn-on switching loss – up to 46.6% at 150°C, compared to the SiC MOSFET.


1997 ◽  
Vol 473 ◽  
Author(s):  
Heng-Chih Lin ◽  
Edwin C. Kan ◽  
Toshiaki Yamanaka ◽  
Simon J. Fang ◽  
Kwame N. Eason ◽  
...  

ABSTRACTFor future CMOS GSI technology, Si/SiO2 interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, change the gate oxide Fowler-Nordheim tunneling behavior. In this research, we used a simple two-spheres model and a three-dimensional Laplace solver to simulate the electric field and the tunneling current in the oxide region. Our results show that both quantities are strong functions of roughness spatial wavelength, associated amplitude, and oxide thickness. We found that RMS roughness itself cannot fully characterize surface roughness and that roughness has a larger effect for thicker oxide in terms of surface electric field and tunneling behavior.


2021 ◽  
Vol 11 (15) ◽  
pp. 7057
Author(s):  
Lin Wang ◽  
Zhe Cheng ◽  
Zhi-Guo Yu ◽  
De-Feng Lin ◽  
Zhe Liu ◽  
...  

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.


Energies ◽  
2019 ◽  
Vol 12 (13) ◽  
pp. 2512 ◽  
Author(s):  
Xiao Yu ◽  
Fan Yang ◽  
Xing Li ◽  
Shaogui Ai ◽  
Yongning Huang ◽  
...  

A balanced voltage distribution for each break is required for normal operation of a multi-break vacuum circuit breaker (VCB) This paper presented a novel 363 kV/5000 A/63 kA sextuple-break VCB with a series-parallel structure. To determine the static voltage distribution of each break, a 3D finite element method (FEM) model was established to calculate the voltage distribution and the electric field of each break at the fully open state. Our results showed that the applied voltage was unevenly distributed at each break, and that the first break shared the most voltage, about 86.3%. The maximum electric field of the first break was 18.9 kV/mm, which contributed to the reduction of the breaking capacity. The distributed and stray capacitance parameters of the proposed structure were calculated based on the FEM model. According to the distributed capacitance parameters, the equivalent circuit simulation model of the static voltage distribution of this 363 kV VCB was established in PSCAD. Subsequently, the influence of the grading capacitor on the voltage distribution of each break was investigated, and the best value of the grading capacitors for the 363 kV sextuple-break VCB was confirmed to be 10 nF. Finally, the breaking tests of a single-phase unit was conducted both in a minor loop and a major loop. The 363 kV VCB prototype broke both the 63 kA and the 80 kA short circuit currents successfully, which confirmed the validity of the voltage sharing design.


2020 ◽  
Vol 1004 ◽  
pp. 776-782
Author(s):  
Kosuke Uchida ◽  
Toru Hiyoshi ◽  
Yu Saito ◽  
Hiroshi Egusa ◽  
Tatsushi Kaneda ◽  
...  

1200 V / 200 A V-groove trench MOSFET optimized to achieve low power loss, high oxide reliability under a drain bias condition and high avalanche ruggedness is shown in this paper. We revealed a relationship between the lifetime under a high temperature reverse bias condition and the oxide electric field. In accordance with the results of the test, the 1200 V / 200 A trench MOSFET showed an improvement in the tradeoff between the on-resistance and oxide electric field with the presence of current spreading layers. In order to obtain low on-resistance and high avalanche ruggedness at the same time, buried guard ring structures, which made the blocking voltage of the edge termination area higher than that of the active area, was developed. The fabricated MOSFETs demonstrated a low specific on-resistance of 3.1 mΩ cm2. A predicted lifetime of 200 years under a high temperature drain bias condition of 1200 V was achieved by the optimized design. A short circuit withstand time of 6 μs and a high avalanche energy of 7.8 J/cm2 were shown.


2020 ◽  
Vol 1004 ◽  
pp. 783-788
Author(s):  
Ki Jeong Han ◽  
Ajit Kanale ◽  
B. Jayant Baliga ◽  
Subhashish Bhattacharya

The electrical characteristics of the 1.2-kV rated 4H-SiC accumulation-channel split-gate octagonal cell MOSFET (SG-OCTFET) are experimentally compared with linear, square, hexagonal, octagonal, and compact-octagonal cell topologies. The specific on-resistance of the SG-OCTFET is 52% larger than the conventional linear cell topology. However, the SG-OCTFET has: (i) high-frequency figure-of-merit HFFOM[Ron×Cgd] 9.4×, 6.1×, 2.6×, 2.0×, and 1.8× superior to the square, hex, linear, octagonal, and compact-octagonal cells; (ii) fastest switching performance among all cell topologies, with 26% smaller switching energy loss than the conventional linear cell topology; and (iii) short circuit capability 1.5× longer than the conventional linear cell topology. The SG-OCTFET device is therefore an optimum candidate for high frequency applications of SiC MOSFETs.


2005 ◽  
Vol 23 (3) ◽  
pp. 693-706 ◽  
Author(s):  
B. Zhao ◽  
W. Wan ◽  
L. Liu

Abstract. The responses of Equatorial Ionization Anomaly (EIA) to the superstorms of October-November 2003 were investigated using the total electron content (TEC) measured with global positioning system (GPS) receivers in China, Southeast Asia, Australian (CSAA), and the American regions. Enhanced EIA was seen to be correlated with the southward turning of the interplanetary magnetic field Bz. In both the CSAA and American regions, EIA was intensified, corresponding to a large increase in the F-layer peak height (hmF2) measured by ionosonde and digisonde at middle and equatorial latitudes. However, the enhanced EIA was shown to be more significant during the daytime in the American region, which was associated with a series of large substorms when Bz was stable southward. The prompt penetration electric field and the wind disturbances dynamo electric field are suggested to be responsible for this observation according to current theory, although some features cannot be totally decipherable. Both the ionogram and magnetometer data show the existence of a weak shielding effect whose effect still needs further study. A clear asymmetric ionospheric response was shown in our TEC observations, even though it was only one month after autumnal equinox. The southern EIA crest was totally obliterated on 29 and 30 October in the CSAA region and on 31 October in the American region. Ion temperatures from the Defense Meteorological Satellite Program (DMSP) spacecraft revealed that the unequal energy injection at the polar region might be the reason for this effect. It is concluded that different physical processes have varying degrees of importance on the evolution of EIA in the CSAA and American regions.


2007 ◽  
Vol 253 (14) ◽  
pp. 5980-5984 ◽  
Author(s):  
Qilong Wang ◽  
Hui Mu ◽  
Xiaobing Zhang ◽  
Wei Lei ◽  
Jinchan Wang ◽  
...  

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