scholarly journals Cache coherency controller for MESI protocol based on FPGA

2021 ◽  
Vol 11 (2) ◽  
pp. 1043
Author(s):  
Mays K. Faeq ◽  
Safaa S. Omran
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Main Memory ◽  
Test Results ◽  
Description Language ◽  
Cache Consistency ◽  
Hardware Description ◽  
Cache Coherency ◽  
Protocol Test ◽  
Multi Core Processor

In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultanously for more than one job or all the cores working in parallel for the same job. All cores are similar in their design, and each core has its own cache memory, while all cores shares the same main memory. So if one core requestes a block of data from main memory to its cache, there should be a protocol to declare the situation of this block in the main memory and other cores.This is called the cache coherency or cache consistency of multi-core. In this paper a special circuit is designed using very high speed integrated circuit hardware description language (VHDL) coding and implemented using ISE Xilinx software. The protocol used in this design is the modified, exclusive, shared and invalid (MESI) protocol. Test results were taken by using test bench, and showed all the states of the protocol are working correctly.

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

A modeling method of algorithm-hardware based on SysML

2021 ◽  
Author(s):  
Liu Yue ◽  
Zhao Chun ◽  
Zhang Lin
Keyword(s):  
Graphical Models ◽  
Integrated Circuit ◽  
High Speed ◽  
System Modeling ◽  
Modeling Method ◽  
Description Language ◽  
Hardware Description ◽  
Circuit And System ◽  
Graphical System ◽  
Hardware Circuit

In the process of complex product design, modeling in different fields and different disciplines is often involved. Designers often face many different development kits, platforms, and theories, among which significant differences exist. Especially in the process of algorithm-hardware implementation, it is necessary to have mastery of the knowledge including algorithm, hardware, circuit, and system engineering. In this paper, a modeling method of algorithm-hardware based on SysML is proposed to reduce the difficulty of algorithm-hardware modeling. By using the method, the designers who do not know the knowledge of hardware can also easily build the algorithm-hardware model. In this method, a method of graphical system modeling based on SysML is used, where the elements of the algorithm-hardware model are described by SysML graphical models. Then, the SysML graphical models are converted to Very-High-Speed Integrated Circuit Hardware Description Language. At last, a detecting algorithm of random number is complemented by the modeling method in this paper and the simulation results are presented at the conclusion.

Power and Vibration of Electrostatic Precipitator Control Based on FPGA

2014 ◽  
Vol 1037 ◽  
pp. 244-247
Author(s):  
Zi Sheng Zhang ◽  
Chun Sheng Wang ◽  
Yi Wang ◽  
Zhan You Wang ◽  
Deng Yuan Song
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Electrostatic Precipitator ◽  
Description Language ◽  
Simulation Test ◽  
High Voltage Power Supply ◽  
Optimization Control ◽  
Field Programmable ◽  
Hardware Description ◽  
Fpga Chip

In order to improve the automation level of the electrostatic precipitator, we used Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) language to compile, emulate and optimize the control system of power source and vibration. In the design of Quartus platform, we used EP1C3T144C8 Field Programmable Gate Array (FPGA) chip to realize high voltage power supply, alarm and protection system. We also realized the compilation and simulation test of each part’s function of 20 s rapping and 40 min rapping cycle. At the same time, we recorded the waveform of simulation. It demonstrated that the validity of the relevant VHDL compilation. We used this method to achieve the optimization control of the electrostatic precipitator operating parameters. It has a strong practicability.

scholarly journals Design and Implementation of Radix 8 Booth Encoding Multiplier for Low Area and High-Speed Applications

2021 ◽  
Vol 9 (12) ◽  
pp. 862-864
Author(s):  
Mutyala Sri Anantha Lakshmi
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Description Language ◽  
Delay Reduction ◽  
Low Area ◽  
Booth Multiplier ◽  
Design And Implementation ◽  
Area Reduction ◽  
Hardware Description ◽  
Very High

Abstract: In this paper, we present the design and implementation of the Radix 8 Booth Encoding Multiplier. There are many multipliers in existence in which Radix 8 Booth Encoding Multiplier offers a decrease in area and provides high speed due to its diminution in the number of partial products. This project is designed and simulated on Xilinx ISE 14.7 version software using VHDL (Very High Speed Integrated Circuit Hardware Description Language). Simulation results show area reduction by 33.4% and delay reduction by 45.9% as compared to the conventional method. Keywords: Booth Multiplier, Radix 8, Partial Product

scholarly journals Support Vector Machine working on FPGA and the segmentation method of brain MR screening

2017 ◽  
Vol 4 (3) ◽  
pp. 120 ◽  
Author(s):  
Fatih Şişik ◽  
Eser Sert
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Support Vector ◽  
Segmentation Method ◽  
Description Language ◽  
Field Programmable ◽  
Hardware Description ◽  
Very High

Alan Programlanabilir Kapı Dizileri (Field Programmable Gate Array-FPGA) programlanabilir sayısal bloklar ve bağlantılarını içeren cihazlar olup çok esnek ve hızlı çalışabilme özelliklerine sahiptir. Programlanabilen bu sayısal kapılar sayesinde karmaşık tasarımlar kolay bir şekilde geliştirilebilmektedir. FPGA’lar küçük boyutlarda olup bilgisayardan bağımsız mobil olarak ve bilgisayarlardan daha yüksek hızlarda çalışabilmektedirler. Veri madenciliğinin görevlerinden biri olan sınıflandırma probleminin çözümü için geliştirilmiş önemli makine öğrenimi algoritmalarından biri Destek Vektör Makineleri’ dir. Literatürde Destek Vektör Makineleri’ nin diğer birçok tekniğe göre daha başarılı sonuçlar verdiği kanıtlanmıştır. Tümör analizi, yüz tanıma, robotik göz oluşturma gibi konular, araştırmacıların görüntü işleme alanında yoğun olarak üzerinde çalıştıkları güncel, önemli ve zor problemlerden bazılarıdır. Bilgisayarda yapılan tümör analizinde, grafik ve resimlerin işlenmesinde yavaş işlem yapma ve aynı zamanda mobil olmama sorunlarından, FPGA donanımı ile görüntü işlemede bu sorunların üstesinden gelinmektedir. Bu çalışmada FPGA donanımında çalışan destek vektör makinası kullanılarak daha gerçekçi tümör analizi yapılarak tümörlü bölgelerin bulunması ve gerekli analiz sonuçlarının gösterilmesi amaçlanmaktadır. Böylece sağlık alanında da kullanılabilecek yararlı bir donanımın tasarımı gerçekleştirilecektir. Dolayısıyla gömülü sistemlerle anlatılan bu işlem süreçlerini gerçekleştiren çalışma sayısı çok az olduğundan çalışma özgün değer taşımaktadır. Buna ek olarak, FPGA’ ya özgü donanım tanımlama dillerinden biri olan Çok Yüksek Hızlı Tümleşik Devre Tanımlama Dili (Very High Speed Integrated Circuit  Hardware Description Language- VHDL) kullanılacaktır. Bölütleme sonucunun değerlendirilmesi için Uniformity Measure (UM) kullanılmıştır. UM değerlendirme sonucunun başarılı olduğu görülmüştür. Anahtar Kelimeler: Alan Programlanabilir Kapı Dizileri, FPGA, çok yüksek hızlı tümleşik devre tanımlama dili, vhdl, segmentasyon, destek vektör makinesi

scholarly journals Switching pulse generation for DC-DC boost converter using Xilinx-ISE with FPGA processor

2020 ◽  
Vol 10 (2) ◽  
pp. 1722
Author(s):  
R. Palanisamy ◽  
C. S. Boopathi ◽  
K. Selvakumar ◽  
K. Vijayakumar
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Dynamic Environment ◽  
Boost Converter ◽  
Pulse Generation ◽  
Description Language ◽  
Course Of Action ◽  
Hardware Description ◽  
Complex Circuits ◽  
Very High

This paper explains steps to generate switching pulse using Xilinx-ISE with FPGA processor for DC-DC boost converter. The switching pulse generated using Very high speed integrated circuit Hardware Description Language (VHDL) with Xilinx-ISE. VHDL is a programming language, which is used to model and design any complex circuits in a dynamic environment. This paper gives the course of action for generation of switching pulses for dc-dc boost converter using Xilinx-ISE and matlab simulink. The switching pulse generated using Xilinx-ISE with FPGA-Spartan 6 processor compared with switching pulse generated using matlab.

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