1.5-V CMOS Current Multiplier/Divider
2018 ◽
Vol 8
(3)
◽
pp. 1478
◽
Keyword(s):
A circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented. It is based on the use of a compact current quadratic cell able to operate at low supply voltage. The proposed circuit is designed and simulated for implementing in TSMC 0.25-m CMOS technology with a single supply voltage of 1.5 V. Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 W, and -3dB small-signal frequency of about 245 MHz.
2016 ◽
Vol 25
(06)
◽
pp. 1650066
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Keyword(s):
2014 ◽
Vol 23
(01)
◽
pp. 1450004
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2015 ◽
Vol 645-646
◽
pp. 1308-1313
Keyword(s):
2018 ◽
Vol 27
(13)
◽
pp. 1850206
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Keyword(s):
2020 ◽
Vol 10
(6)
◽
pp. 5642
2014 ◽
Vol 17
(1)
◽
pp. 62-70
2017 ◽
Vol 26
(08)
◽
pp. 1740003
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Keyword(s):