scholarly journals Performance Enhancement of Bidirectional NOC Router With and Without Contention for Reconfigurable Coarse Grained Architecture

2018 ◽  
Vol 11 (3) ◽  
pp. 1068
Author(s):  
Yazhinian Sougoumar ◽  
Tamilselvan Sadasivam
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Performance Enhancement ◽  
Round Robin ◽  
Vital Role ◽  
Coarse Grained ◽  
Output Channel ◽  
Crossbar Switches ◽  
Static Ram ◽  
On Chip

<p>Network on Chip (NoC) router plays a vital role in System on Chip (SoC) applications. Routing operation is difficult to perform inside the SoC chip. Because it contains millions of chips in one single Integrated Circuit (IC), in which every chip consists of millions of transistors. Hence NoC router is designed to enable efficient routing operation in the SoC board.  NoC router consists of Network Interconnects (NI), Crossbar Switches, arbiters, a routing logic and buffers. Conventional unidirectional router is designed by priority based Round Robin Arbiter (RRA). It produces more delay to find the priority, which comes from various input channels and more area is consumed in unidirectional router. Also if any path failure occurs, it cannot route the data through other output channel. To overcome this problem, a novel bidirectional NoC router with and without contention is proposed, which offers less area and high speed than the existing unidirectional router. A novel bidirectional NoC router consists of round robin arbiter, Static RAM, switch allocator, virtual channel allocator and crossbar switch. The proposed bidirectional router can route the data from any input channel to each and every output channel. So it avoids conflict situation and path failure problems. If any path fails, immediately it will take the alternative path through the switch allocator. The proposed routing scheme is applied into the coarse grained architecture for improving the speed of the interconnection link between two processing elements. Simulation is performed by ModelSim6.3c and synthesis is carried out by Xilinx10.1.</p>

Optimized High Power GaN Transistors

2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000195-000199
Author(s):  
J. Roberts ◽  
A. Mizan ◽  
L. Yushyna
Keyword(s):  
High Speed ◽  
Figure Of Merit ◽  
Printed Circuit Board ◽  
Heat Removal ◽  
Vital Role ◽  
Circuit Board ◽  
Die Structure ◽  
Power Switches ◽  
On Chip ◽  
Very High

GaN transistors intended for use at 600–900 V and that are capable of providing of 30–100 A are being introduced this year. These devices have a substantially better switching Figure-of-Merit (FOM) than silicon power switches. Rapid market acceptance is expected leading to compound annual growth rates of 85 %. However these devices present new packaging challenges. Their high speed combined with the very high current being switched demands that very low inductance packaging must be combined with highly controlled drive circuitry. While convention, and the usually vertical power device die structure, has largely determined power transistor package formats in the past, the lateral nature of the today GaN devices requires the use of new package types. The new packages have to operate at high temperatures while providing effective heat removal, low inductance, and low series resistance. Because GaN devices are lateral they require the package metal tracks to be integrated within the on-chip tracks to carry the current away from the thin on-chip metal tracks. The new GaN devices are available in two formats: one for use in embedded modular assemblies and the other for use mounted upon conventional circuit board systems. The package intended for discrete printed circuit board (PCB) assemblies has a top side cooling option that simplifies the thermal interface to the heat sink. The paper describes the die layout including the added copper tracks. The corresponding package elements that interface directly with the surface of the die play a vital role in terms of the current handling. They also provide the interface to the external busbars that allow the package to be mounted within, or on PCB. The assembly has been subject to extensive thermal analysis and the performance of a 30 A, 650 V transistor is described.

scholarly journals A Comparison between off and On-Chip Injection Locking in a Photonic Integrated Circuit

Photonics ◽  
2019 ◽  
Vol 6 (4) ◽  
pp. 103 ◽  
Author(s):  
Alison Perrott ◽  
Ludovic Caro ◽  
Mohamad Dernaika ◽  
Frank Peters
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Power Spectra ◽  
Dynamical Behaviour ◽  
Injection Locking ◽  
Semiconductor Diode ◽  
Photonic Integrated Circuit ◽  
Semiconductor Diode Laser ◽  
Spectrum Analyser ◽  
On Chip

The mutual and injection locking characteristics of two integrated lasers are compared, both on and off-chip. In this study, two integrated single facet slotted Fabry–Pérot lasers are utilised to develop the measurement technique used to examine the different operational regimes arising from optically locking a semiconductor diode laser. The technique employed used an optical spectrum analyser (OSA), an electrical spectrum analyser (ESA) and a high speed oscilloscope (HSO). The wavelengths of the lasers are measured on the OSA and the selected optical mode for locking is identified. The region of injection locking and various other regions of dynamical behaviour between the lasers are observed on the ESA. The time trace information of the system is obtained from the HSO and performing the FFT (Fast Fourier Transform) of the time traces returns the power spectra. Using these tools, the similarities and differences between off-chip injection locking with an isolator, and on-chip mutual locking are examined.

CMOS INTEGRATED CIRCUIT CONTROLLERS FOR SWITCHING POWER CONVERTERS

2004 ◽  
Vol 13 (04) ◽  
pp. 789-811
Author(s):  
EDUARD ALARCÓN ◽  
GERARD VILLAR ◽  
ALBERTO POVEDA
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
High Performance ◽  
Power Converters ◽  
Correct Operation ◽  
Case Examples ◽  
Cmos Integrated Circuit ◽  
Switching Power ◽  
Switching Power Converters ◽  
On Chip

Two case examples of high-speed CMOS microelectronic implementations of high-performance controllers for switching power converters are presented. The design and implementation of a current-programmed controller and a general-purpose feedforward one-cycle controller are described. The integrated circuit controllers attain high-performance by means of using current-mode analog signal processing, hence allowing high switching frequencies that extend the operation margin compared to previous designs. Global layout-extracted transistor-level simulation results for 0.8 μm and 0.35 μm standard CMOS technologies confirm both the correct operation of the circuits in terms of bandwidth as well as their functionality for the control of switching power converters. The circuits may be used either as standalone IC controllers or as controller circuits that are technology-compatible with on-chip switching power converters and on-chip loads for future powered systems-on-chip.

scholarly journals Passivity Preserving Model Order Reduction Using the Reduce Norm Method

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 964
Author(s):  
Namra Akram ◽  
Mehboob Alam ◽  
Rashida Hussain ◽  
Asghar Ali ◽  
Shah Muhammad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Model Order Reduction ◽  
High Speed ◽  
Order Reduction ◽  
Reliable Operation ◽  
Model Order ◽  
Reduced Order ◽  
Reduction Methods ◽  
On Chip

Modeling and design of on-chip interconnect, the interconnection between the components is becoming the fundamental roadblock in achieving high-speed integrated circuits. The scaling of interconnect in nanometer regime had shifted the paradime from device-dominated to interconnect-dominated design methodology. Driven by the expanding complexity of on-chip interconnects, a passivity preserving model order reduction (MOR) is essential for designing and estimating the performance for reliable operation of the integrated circuit. In this work, we developed a new frequency selective reduce norm spectral zero (RNSZ) projection method, which dynamically selects interpolation points using spectral zeros of the system. The proposed reduce-norm scheme can guarantee stability and passivity, while creating the reduced models, which are fairly accurate across selected narrow range of frequencies. The reduced order results indicate preservation of passivity and greater accuracy than the other model order reduction methods.

Microfabrication of Field Emission Devices for Vacuum Integrated Circuits using Orientation Dependent Etching

1986 ◽  
Vol 76 ◽  
Author(s):  
G. J. Campisi ◽  
H. F. Gray
Keyword(s):  
Integrated Circuits ◽  
Field Emission ◽  
Integrated Circuit ◽  
High Speed ◽  
Radius Of Curvature ◽  
Hostile Environment ◽  
Electron Sources ◽  
Submicron Scale ◽  
On Chip ◽  
Extraction Electrode

ABSTRACTVacuum integrated circuits and field emission (FE) devices with geometries on the micron and submicron scale have been discussed as alternatives to solid state devices for high speed and hostile environment application as well as for miniature electron sources for CRTs. These miniaturized vacuum devices have been developed on the basis of the advances in micromachining technology, i.e. orientation-dependent etching (ODE) of lithographically patterned silicon. This paper describes the ODE methods used to fabricate pyramidal electron emitter points 1.5 μm high, with radius of curvature of 20 to 100 nm from <100> silicon. In order to reduce operating voltages, an integral extraction electrode (grid) was fabricated by a self-aligned technique. With a single gate mask level the extraction and planar collector structures were fabricated on chip, to form a planar vacuum triode. The final mask step provided the flexibility for fabricating a variety of planar vacuum integrated circuit elements.

scholarly journals Electrically Driven Micro- and Nano-Scale Semiconductor Light Sources

2019 ◽  
Vol 9 (4) ◽  
pp. 802 ◽  
Author(s):  
You-Shin No
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Data Communication ◽  
Essential Element ◽  
Light Sources ◽  
Photonic Integrated Circuit ◽  
Power Efficient ◽  
Light Emitting Devices ◽  
Nano Scale ◽  
On Chip

Emerging optical technology capable of addressing the limits in modern electronics must incorporate unique solutions to bring about a revolution in high-speed, on-chip data communication and information processing. Among the possible optical devices that can be developed, the electrically driven, ultrasmall semiconductor light source is the most essential element for a compact, power-efficient photonic integrated circuit. In this review, we cover the recent development of the electrically driven light-emitting devices based on various micro- and nano-scale semiconductor optical cavities. We also discuss the recent advances in the integration of these light sources with passive photonic circuits.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

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