A General Structure and High-Performance Dual-Edge Triggered Level Converting Flip–Flop Based on BiCMOS

2020 ◽  
Vol 15 (1) ◽  
pp. 136-141
Author(s):  
Xianghong Zhao ◽  
Jieyu Zhao ◽  
WeiMing Cai
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Supply Voltage ◽  
Design Method ◽  
General Structure ◽  
Effective Solution ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Logic Functions ◽  
Structure And Design

Dual supply voltage scheme provides very effective solution to cut down power consumption in digital integrated circuits design, where level converting flip–flops (LCFF) are the key component circuits. In this paper, a new general structure and design method for dual-edge triggered LCFF based on BiCMOS is proposed, according to that PNP-PNP-DELCFF and NPN-NPN-DELCFF are designed. The experiments carried out by Hspice using TSMC 180 nm show proposed circuits have correct logic functions. Compared to counterparts, proposed PNP-PNP-DELCFF gains improvements of 6.7%, 96.0%, 86.0% and 28.5% in D-Q Delay, 50.0%, 16.0%, 12.6% and 10.8% in product of delay and power (PDP), respectively. NPN-NPN-DELCFF gains improvements of 5.1%, 93.0%, 83.2% and 26.5% in D-Q Delay, 39.7%, 7.9%, 5.0% and 3.4% in PDP, respectively. Furthermore, proposed circuits have better drive ability.

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

2015 ◽  
Vol 24 (07) ◽  
pp. 1550094 ◽  
Author(s):  
Jizhong Shen ◽  
Liang Geng ◽  
Xuexiang Wu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Clock Cycle ◽  
Control Technique ◽  
Switching Activity ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Deep Impact ◽  
Power Pulse

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

A 4H-SiC Bipolar Technology for High-Temperature Integrated Circuits

2013 ◽  
Vol 10 (4) ◽  
pp. 155-162 ◽  
Author(s):  
L. Lanni ◽  
B. G. Malm ◽  
C.-M. Zetterling ◽  
M. Östling
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Low Voltage ◽  
Supply Voltage ◽  
Bipolar Transistors ◽  
Digital Integrated Circuits ◽  
Successful Operation ◽  
Bipolar Technology ◽  
Propagation Delays ◽  
Interconnect Systems

A 4H-SiC bipolar technology suitable for high-temperature integrated circuits is tested with two interconnect systems based on aluminum and platinum. Successful operation of low-voltage bipolar transistors and digital integrated circuits based on emitter coupled logic (ECL) is reported from 27°C up to 500°C for both the metallization systems. When operated on −15 V supply voltage, aluminum and platinum interconnect OR-NOR gates showed stable noise margins of about 1 V and asymmetric propagation delays of about 200 and 700 ns in the whole temperature range for both OR and NOR output. The performance of aluminum and platinum interconnects was evaluated by performing accelerated electromigration tests at 300°C with current density of about 1 MA/cm2 on contact chains consisting of 10 integrated resistors. Although in both cases the contact chains failed after less than one hour, different failure mechanisms were observed for the two metallization systems: electromigration for the aluminum system and poor step coverage and via filling for the platinum system.

scholarly journals Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1550011
Author(s):  
Neeraja Jagadeesan ◽  
B. Saman ◽  
M. Lingalugari ◽  
P. Gogna ◽  
F. Jain
Keyword(s):  
Integrated Circuits ◽  
Quantum Well ◽  
Logic Gates ◽  
Digital Integrated Circuits ◽  
Short Channel ◽  
Flip Flop ◽  
Coupled Channels ◽  
Threshold Voltages ◽  
Sequential Logic ◽  
Quantum Well Devices

The spatial wavefunction-switched field-effect transistor (SWSFET) is one of the promising quantum well devices that transfers electrons from one quantum well channel to the other channel based on the applied gate voltage. This eliminates the use of more transistors as we have coupled channels in the same device operating at different threshold voltages. This feature can be exploited in many digital integrated circuits thus reducing the count of transistors which translates to less die area. The simulations of basic sequential circuits like SR latch, D latch and flip flop are presented here using SWSFET based logic gates. The circuit model of a SWSFET was developed using Berkeley short channel IGFET model (BSIM 3).

A Cost-Effective Solution for Testing High-Performance Integrated Circuits

2021 ◽  
Vol 11 (4) ◽  
pp. 557-564
Author(s):  
Nandish Bharat Thaker ◽  
Rakesh Ashok ◽  
Sarath Manikandan ◽  
Nandakumar Nambath ◽  
Shalabh Gupta
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Cost Effective ◽  
Effective Solution

scholarly journals Low Power and High Performance MTCMOS Conditional Discharge Flip Flop

2019 ◽  
Vol 8 (6S2) ◽  
pp. 341-345
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Leakage Power ◽  
Battery Life ◽  
Flip Flop ◽  
Circuit Performance ◽  
Processing Information ◽  
Conditional Discharge ◽  
Standby Mode

Utilization in high-performance integrated circuits has been one of the most severe limitations in models in recent years.. Conditional discharge flip flop (CDFF) related to one of the earliest pulses caused flipflop reduces internal switching activities as that of existing explicit pulse triggered Data close to output flipflop (Ep-DCO). Registers are the main parts for processing information eg: in counters, accumulators etc.,. Implementation of these registers using CDFF can achieve low power consumption and high performance. MTCMOS (multi threshold CMOS) technique saves the leakage power during standby mode operations and hence, enhances the circuit performance for long battery life applications. We find that, using both MTCMOS and conditional discharge technique in flip flop, improves the performance and also consumes low power. In this paper, we simulate CDFF and the proposed MTCMOS CDFF to prove that MTCMOS CDFF is the best among the fastest pulse triggered flipflops. We also implement an application 4 bit shift register using proposed MTCMOS conditional discharge flip flop

Proficient Technique for High Performance Very Large-Scale Integration System to Amend Clock Gated Dual Edge Triggered Sense Amplifier Flip-Flop with Less Dissipation of Power Leakage

2021 ◽  
Vol 16 (4) ◽  
pp. 602-611
Author(s):  
A. N. Duraivel ◽  
B. Paulchamy ◽  
K. Mahendrakan
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Supply Voltage ◽  
Clock Cycle ◽  
The State ◽  
High Threshold ◽  
Clock Signal ◽  
Signal Transfer ◽  
Flip Flop ◽  
Sleep Transistors

Clocked flip flops are used to memory in synchronous or clocked series networks, adjusting the individual clock signal status. Therefore, at these times of clock signal transfer, the state of the memory unit and the state of the whole electrical structure change. It’s only during signal transfer that the key to a flip-flop being correctly operated. Two transitions from 0 and 1 are followed by a clock pulse, and 1 to 0. The pulse shift is defined by the positive and negative sides of the pulse. The data on or off the clock cycle edges are recorded by a single-edge trigger flip flop (SETFF), but the flip flop with the double-edge sensor amplifier (DETSAFF). Another common technique for dynamic energy consumption reduced when the device is idle is the clock gating. In this document. Sleep is used to reduce the power of the leakage Here are the following: High threshold voltages sleep transistors are used. Among the supply voltage and VDD the sleep pMOS transistor and the pull-up system and between the network and the ground GND a sleep NMOs Transistor is located. With sleep transistors, CG-SAFF can save up to 30% of its power during zero input switching operation. For different sequential device architecture, the proposed flip-flop may be used.

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