Proficient Technique for High Performance Very Large-Scale Integration System to Amend Clock Gated Dual Edge Triggered Sense Amplifier Flip-Flop with Less Dissipation of Power Leakage

2021 ◽  
Vol 16 (4) ◽  
pp. 602-611
Author(s):  
A. N. Duraivel ◽  
B. Paulchamy ◽  
K. Mahendrakan
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Supply Voltage ◽  
Clock Cycle ◽  
The State ◽  
High Threshold ◽  
Clock Signal ◽  
Signal Transfer ◽  
Flip Flop ◽  
Sleep Transistors

Clocked flip flops are used to memory in synchronous or clocked series networks, adjusting the individual clock signal status. Therefore, at these times of clock signal transfer, the state of the memory unit and the state of the whole electrical structure change. It’s only during signal transfer that the key to a flip-flop being correctly operated. Two transitions from 0 and 1 are followed by a clock pulse, and 1 to 0. The pulse shift is defined by the positive and negative sides of the pulse. The data on or off the clock cycle edges are recorded by a single-edge trigger flip flop (SETFF), but the flip flop with the double-edge sensor amplifier (DETSAFF). Another common technique for dynamic energy consumption reduced when the device is idle is the clock gating. In this document. Sleep is used to reduce the power of the leakage Here are the following: High threshold voltages sleep transistors are used. Among the supply voltage and VDD the sleep pMOS transistor and the pull-up system and between the network and the ground GND a sleep NMOs Transistor is located. With sleep transistors, CG-SAFF can save up to 30% of its power during zero input switching operation. For different sequential device architecture, the proposed flip-flop may be used.

Design of Low Power Dual Dynamic Node Flip-Flop Using Sleep Transistor with NMOS

2015 ◽  
Vol 4 (3) ◽  
pp. 178
Author(s):  
Ajeesh Kumar ◽  
N. Saraswathi
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Circuits ◽  
Flip Flop ◽  
Sleep Transistors ◽  
Power Delay Product ◽  
Charge Mode ◽  
Logic Level

This paper introduces a Low Power Dual DynamicNode FlipFlop(DDFF) using Sleep Transistor with NMOS. Theproposed design retains the logic level till the end of evaluation and pre-charge mode. The low power DDFF architecturethat combines the advantages of dynamic and static CMOSstructures. The Sleep Transistors approach are used for leakagepower reduction. It reduces leakage current in ideal mode.The performance of the proposed flip flop was compared withthe conventional dual dynamic node flip flop (DDFF) in 90nmCMOS technology with 1.2v supply voltage at room temperatures.Also, conventional DDFF and DDFF using Sleep Transistor withNMOS are compared with other complicated designs and realizesby a 4-bit Johnson up and down counter. The performanceimprovements indicates that the proposed designs are suited formodern high-performance CMOS circuits where leakage powerand power delay product overhead are of major concern

scholarly journals Design and Implementation of High Performance PPSK demodulator in Biomedical Implant

2021 ◽  
Author(s):  
Hima Bindu Katikala ◽  
G.Ramana Murthy ◽  
Yatavakilla Amarendra Nath
Keyword(s):  
Low Power ◽  
Hearing Aids ◽  
Data Transmission ◽  
High Performance ◽  
Large Scale ◽  
Analog Circuit ◽  
Supply Voltage ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass

Abstract The important challenge for the realization of hearing aids is small size, low cost, low power consumption and better performance, etc. Keeping these requirements in view this work concentrates on the VLSI (Very Large Scale Integrated) implementation of analog circuit that mimic the PPSK (Passive Phase Shift Keying) demodulator with low pass filter. This research deals with RF Cochlear implant circuits and their data transmission. A PPSK modulator is used for uplink data transmission in biomedical implants with simultaneous power, data transmission This paper deals about the implementation of PPSK demodulator with related circuits and low pass filter which are used in cochlear implants consumes low power and operates at 14MHz frequency. These circuits are designed using FINFET 20nm technology with 0.4v DC supply voltage. The performance of proposed design over the previous design is operating at low threshold voltage, reduces static leakage currents and often observed greater than 30 times of improvement in speed performance

A General Structure and High-Performance Dual-Edge Triggered Level Converting Flip–Flop Based on BiCMOS

2020 ◽  
Vol 15 (1) ◽  
pp. 136-141
Author(s):  
Xianghong Zhao ◽  
Jieyu Zhao ◽  
WeiMing Cai
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Supply Voltage ◽  
Design Method ◽  
General Structure ◽  
Effective Solution ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Logic Functions ◽  
Structure And Design

Dual supply voltage scheme provides very effective solution to cut down power consumption in digital integrated circuits design, where level converting flip–flops (LCFF) are the key component circuits. In this paper, a new general structure and design method for dual-edge triggered LCFF based on BiCMOS is proposed, according to that PNP-PNP-DELCFF and NPN-NPN-DELCFF are designed. The experiments carried out by Hspice using TSMC 180 nm show proposed circuits have correct logic functions. Compared to counterparts, proposed PNP-PNP-DELCFF gains improvements of 6.7%, 96.0%, 86.0% and 28.5% in D-Q Delay, 50.0%, 16.0%, 12.6% and 10.8% in product of delay and power (PDP), respectively. NPN-NPN-DELCFF gains improvements of 5.1%, 93.0%, 83.2% and 26.5% in D-Q Delay, 39.7%, 7.9%, 5.0% and 3.4% in PDP, respectively. Furthermore, proposed circuits have better drive ability.

scholarly journals Text Rewriting Improves Semantic Role Labeling

2014 ◽  
Vol 51 ◽  
pp. 133-164 ◽  
Author(s):  
K. Woodsend ◽  
M. Lapata
Keyword(s):  
Gold Standard ◽  
High Performance ◽  
Large Scale ◽  
State Of The Art ◽  
The State ◽  
Semantic Role ◽  
Semantic Role Labeling ◽  
Comparable Corpora ◽  
Rewrite Rules ◽  
Model Training

Large-scale annotated corpora are a prerequisite to developing high-performance NLP systems. Such corpora are expensive to produce, limited in size, often demanding linguistic expertise. In this paper we use text rewriting as a means of increasing the amount of labeled data available for model training. Our method uses automatically extracted rewrite rules from comparable corpora and bitexts to generate multiple versions of sentences annotated with gold standard labels. We apply this idea to semantic role labeling and show that a model trained on rewritten data outperforms the state of the art on the CoNLL-2009 benchmark dataset.

High-Speed Low-Power Bulk-Controlled Sense-Amplifier D Flip-Flop

2015 ◽  
Vol 713-715 ◽  
pp. 1042-1047
Author(s):  
Xiao Ying Deng ◽  
Yan Yan Mo ◽  
Jian Hui Ning
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Large Scale ◽  
Supply Voltage ◽  
Operating Conditions ◽  
Cmos Process ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Operation Speed ◽  
Circuits Vlsi

With the development of digital very large scale integrated circuits (VLSI), how to reduce the power dissipation and improve the operation speed are two aspects among the most concerned fields. Based on sense amplifier technology and bulk-controlled technique, this paper proposes a bulk-controlled sense-amplifier D flip-flop (BCSADFF). Firstly, this flip-flop can change the threshold voltage of the NMOS by inputting control signals from the substrate so as to control the operating current. Secondly, the traditional RS flip-flop composed of two NAND gates is improved to a couple of inverters based on pseudo-PMOS dynamic technology. Therefore, the proposed BCSADFF can both effectively reduce the power dissipation and improve the circuit speed. Thirdly, the designed BCSADFF can work normally with ultra-dynamic voltage scaling from 1.8 V to 0.6V for SMIC 0.18-um standard CMOS process. Lastly, the Hspice simulation result shows that, compared with the traditional sense-amplifier D flip-flop (SADFF), the power dissipation of the BCSADFF is significantly reduced under the same operating conditions. When the power supply voltage is 0.9V, the power dissipation and delay of the SADFF is 6.54uW and 0.386ns while that of the proposed BCSADFF is 2.09uW and 0.237ns.

scholarly journals State Support for Shared Research Facilities: Any Results Yet?

2021 ◽  
Vol 16 (3) ◽  
pp. 416-440
Author(s):  
Kirill Kalyuzhnyi
Keyword(s):  
Growth Rate ◽  
High Performance ◽  
Large Scale ◽  
High Growth ◽  
High Growth Rate ◽  
The State ◽  
Ministry Of Education ◽  
Average Value ◽  
Monitoring Tools ◽  
Research Facilities

Introduction. The article is based on the findings collected by monitoring the Russian Сore Shared Research Facilities (CSRF) and Large-Scale Research Facilities (LSRF). The monitoring is carried out annually by RIEPL specialists on behalf of the Ministry of Education and Science of Russia. The author suggests that the CSRFs and LSRFs sponsored by the state under the federal target programme Research and Development in Priority Areas of Development in Science and Technology in Russia for 2014-2021 stand to deliver high performance across the key indicators, namely the number of external users, value of the work performed for their benefit, and actual workload on research equipment in the interests of external users. Monitoring Tools. The empirical basis of the study is the reporting data for 2014-2020, obtained from CSRFs and LSRFs representatives through the use of the web forms on the portal http://ckp-rf.ru. Results. In the group of sponsored CSRFs, the high growth rate in the number of external users and the average value of the work completed was due to the expansion of the range of services through the use of equipment purchased under the Federal Target Programme. The growth rate of the actual workload proved to be lower compared to the other groups. In the group of sponsored LSRFs, only the actual workload values showed some growth. The growth rate in the number of external users was lower compared to the non-sponsored facility group; the growth rate in the value of work performed did not change from the 2014 baseline. It is, therefore, concluded that there is a need to abandon the competitive financing of shared use infrastructure in favour of targeted financing. Conclusion. The results may be useful in assessing the state of the Russian research infrastructure and divising guidelines for its continued support.

scholarly journals Selective Flip-Flop Optimization for Circuit Reliability

2020 ◽  
pp. 337-364
Author(s):  
Mohammad Saber Golanbari ◽  
Mojtaba Ebrahimi ◽  
Saman Kiamehr ◽  
Mehdi B. Tahoori
Keyword(s):  
Large Scale ◽  
Supply Voltage ◽  
Voltage Drop ◽  
Vlsi Circuits ◽  
Optimization Approach ◽  
Voltage Fluctuation ◽  
Flip Flop ◽  
Bias Temperature Instability ◽  
Optimization Methodology ◽  
Critical Components

AbstractThis chapter proposes a selective flip-flop optimization method (Golanbari et al., IEEE Trans Very Large Scale Integr VLSI Syst 39(7):1484–1497, 2020; Golanbari et al., Aging guardband reduction through selective flip-flop optimization. In: IEEE European Test Symposium (ETS) (2015)), in which the timing and reliability of the VLSI circuits are improved by optimizing the timing-critical components under severe impact of runtime variations. As flip-flops are vulnerable to aging and supply voltage fluctuation, it is necessary to address these reliability issues in order to improve the overall system lifetime. In the proposed method, we first extend the standard cell libraries by adding optimized versions of the flip-flops designed for better resiliency against severe Bias Temperature Instability (BTI) impact and/or supply voltage fluctuation. Then, we optimize the VLSI circuit by replacing the aging-critical and voltage-drop critical flip-flops of the circuit with optimized versions to improve the timing and reliability of the entire circuit in a cost-effective way. Simulation results show that incorporating the optimized flip-flops in a processor can prolong the circuit lifetime by 36.9%, which translates into better reliability.This chapter is organized as follows. Section 1 introduces wide-voltage operation reliability issues and motivates the proposed selective flip-flop optimization approach. The impacts of runtime variations on flip-flops are explained in Sect. 2. Consequently, Sect. 3 presents cell-level optimization of the flip-flops. The proposed selective flip-flop optimization methodology is described in Sect. 4, and optimization results are discussed in Sect. 5. Finally, Sect. 7 concludes the chapter.

CHALLENGE OF RUBBER/GRAPHENE COMPOSITES AIMING AT REAL APPLICATIONS

2017 ◽  
Vol 90 (2) ◽  
pp. 225-237 ◽  
Author(s):  
Zhijun Yang ◽  
Baochun Guo ◽  
Liqun Zhang
Keyword(s):  
High Performance ◽  
Large Scale ◽  
State Of The Art ◽  
The State ◽  
Rubber Composites ◽  
The Status

ABSTRACT Graphene has attracted a great deal of interest in recent years, illustrated by its potential in a variety of areas in physics, chemistry, and engineering. Specifically, graphene has opened up exciting possibilities for high-performance and functional rubber composites. Although copious literature deals with the fascinating properties related to graphene, its real (large scale) applications in rubber-based composites have not been approached. We discuss the state of the art in development in processing and the status in understanding of structure/performance relationships. Accordingly, the prospectives and challenges of some real applications of graphene-based rubber composites such as tires and sensors are surveyed and discussed.

A Reliable, Low Power and Nonvolatile MTJ-Based Flip-Flop for Advanced Nanoelectronics

2018 ◽  
Vol 27 (13) ◽  
pp. 1850205 ◽  
Author(s):  
Ramin Rajaei
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Radiation Effects ◽  
Large Scale ◽  
Vlsi Design ◽  
Magnetic Tunnel Junction ◽  
Cmos Technology ◽  
Flip Flop ◽  
Reliability Challenge

Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write operation over the previous MFFs. This magnetic-based logic circuit is based on the previous two-in-one (TIO) MTJ cell that presents the aforementioned attributes. Radiation-induced single event upset, as another reliability challenge, is also taken into consideration for the MFFs and another MFF robust against radiation effects is suggested and evaluated.

scholarly journals Text Rewriting Improves Semantic Role Labeling (Extended Abstract)

2017 ◽  
Author(s):  
Kristian Woodsend ◽  
Mirella Lapata
Keyword(s):  
Gold Standard ◽  
High Performance ◽  
Large Scale ◽  
State Of The Art ◽  
The State ◽  
Semantic Role ◽  
Semantic Role Labeling ◽  
Comparable Corpora ◽  
Rewrite Rules ◽  
Model Training

Large-scale annotated corpora are a prerequisite to developing high-performance NLP systems. Such corpora are expensive to produce, limited in size, often demanding linguistic expertise. In this paper we use text rewriting as a means of increasing the amount of labeled data available for model training. Our method uses automatically extracted rewrite rules from comparable corpora and bitexts to generate multiple versions of sentences annotated with gold standard labels. We apply this idea to semantic role labeling and show that a model trained on rewritten data outperforms the state of the art on the CoNLL-2009 benchmark dataset.

Sign in / Sign up

Export Citation Format

Share Document