Analysis of Leakage Current and Power Dissipation in 5T SRAM Cell

2016 ◽  
Vol 5 (6) ◽  
pp. 792-797
Author(s):  
Raghav Aggarwal ◽  
Balwinder Raj ◽  
Lakhwinder Singh Teji ◽  
Ritesh Kumar
Keyword(s):  
Leakage Current ◽  
Power Dissipation ◽  
Sram Cell

scholarly journals Implementation and modeling of low power sleepy stack SRAM cell

2019 ◽  
Vol 2 (1) ◽  
pp. 53-56
Author(s):  
Manvinder Sharma ◽  
Dishant Khosla ◽  
Sohni Singh ◽  
Pankaj Palta
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Leakage Current ◽  
Power Dissipation ◽  
Memory Cell ◽  
Threshold Current ◽  
Heat Emission ◽  
Leakage Power ◽  
Sram Cell ◽  
Future Technologies

for the future technologies in which the devices and circuits are integrating more, low power consuming devices are needed. Mostly the reduction of power dissipation work is concentrated on switching and leakage current. However sub threshold current is also a big factor which leads to power consumption especially for memories. In this paper, leakage power of SRAM memory cell is reduced by power gated sleepy stack structure which leads to lesser power dissipation. The power dissipation is reduced to 226 µW with proposed technique compared with power dissipation of conventional 6T SRAM cell which had 740 µW. With lesser power dissipation the circuit can have more battery backup and lesser heat emission

Influence of Overgrown Micropipes in the Active Area of SiC Schottky Diodes on Long Term Reliability

2005 ◽  
Vol 483-485 ◽  
pp. 925-928 ◽  
Author(s):  
Roland Rupp ◽  
Michael Treu ◽  
Peter Türkes ◽  
H. Beermann ◽  
Thomas Scherg ◽  
...  
Keyword(s):  
Leakage Current ◽  
Power Dissipation ◽  
Schottky Diodes ◽  
Physical Structure ◽  
Active Area ◽  
Clear Correlation ◽  
Local Power ◽  
Degradation Mechanisms ◽  
Failure Simulation

Other than open micropipes (MP), overgrown micropipes do not necessarily lead to a^significantly reduced blocking capability of the affected SiC device. However they can lead to a degradation of the device during operation. In this paper the physical structure of overgrown micropipes will be revealed and their contribution to the leakage current will be shown. The possible impact of the high local power dissipation in the surrounding of the overgrown micropipe will be discussed and long term degradation mechanisms will be described. Failure simulation under laboratory conditions shows a clear correlation between the position of overgrown micropipes and the location of destructive burnt spots.

scholarly journals Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1718
Author(s):  
Neha Gupta ◽  
Ambika Prasad Shah ◽  
Sajid Khan ◽  
Santosh Kumar Vishvakarma ◽  
Michael Waltl ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Leakage Power ◽  
Functional Improvement ◽  
Scaling Technique ◽  
Iot Applications ◽  
Sram Cell ◽  
Improved Stability ◽  
Supply Voltage Scaling ◽  
Power Delay Product

This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

2021 ◽  
pp. 2150270
Author(s):  
Jitendra Kumar Mishra ◽  
Lakshmi Likhitha Mankali ◽  
Kavindra Kandpal ◽  
Prasanna Kumar Misra ◽  
Manish Goswami
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Static Noise Margin ◽  
Semiconductor Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Noise

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

Sign in / Sign up

Export Citation Format

Share Document