scholarly journals An Innovative Design solution for minimizing Power Dissipation in SRAM Cell

2017 ◽  
Vol 07 (05) ◽  
pp. 25-28
Author(s):  
Miss. Varsha Phad ◽  
Prof Swati Shetkar
Keyword(s):  
Power Dissipation ◽  
Design Solution ◽  
Innovative Design ◽  
Sram Cell

scholarly journals Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1718
Author(s):  
Neha Gupta ◽  
Ambika Prasad Shah ◽  
Sajid Khan ◽  
Santosh Kumar Vishvakarma ◽  
Michael Waltl ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Leakage Power ◽  
Functional Improvement ◽  
Scaling Technique ◽  
Iot Applications ◽  
Sram Cell ◽  
Improved Stability ◽  
Supply Voltage Scaling ◽  
Power Delay Product

This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

2021 ◽  
pp. 2150270
Author(s):  
Jitendra Kumar Mishra ◽  
Lakshmi Likhitha Mankali ◽  
Kavindra Kandpal ◽  
Prasanna Kumar Misra ◽  
Manish Goswami
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Static Noise Margin ◽  
Semiconductor Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Noise

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

Analysis of Leakage Current and Power Dissipation in 5T SRAM Cell

2016 ◽  
Vol 5 (6) ◽  
pp. 792-797
Author(s):  
Raghav Aggarwal ◽  
Balwinder Raj ◽  
Lakhwinder Singh Teji ◽  
Ritesh Kumar
Keyword(s):  
Leakage Current ◽  
Power Dissipation ◽  
Sram Cell

An I-Ching-TRIZ-Inspired Approach to Design Concept Generation

2009 ◽  
Author(s):  
Duc Truong Pham ◽  
Huimin Liu
Keyword(s):  
Design Concept ◽  
Design Solution ◽  
Concept Generation ◽  
I Ching ◽  
Innovative Design ◽  
New Approach ◽  
Design Concepts ◽  
Aircraft Cabin ◽  
Design Specifications ◽  
Design Solutions

This paper presents a new approach to producing innovative design concepts. The proposed approach involves extending the inventive principles of TRIZ by integrating other TRIZ and TRIZ-inspired tools. The set of inventive principles is then structured according to a framework adapted from I-Ching and represented using TRIZ’s Behaviour-Entity (BE) formalism to which constraints have also been added. The adoption of the BE representation enables a reduction in the amount of repeated information in the inventive principles. A BE pair contains information on a design solution. A Behaviour-Entity-Constraint (BEC) triple additionally has information on constraints on the solution. The BEC representation thus facilitates the retrieval and generation of design solutions from design specifications. The paper uses the problem of laying out seats in an aircraft cabin to illustrate advantages of the proposed approach.

scholarly journals Influence of speed of dispenser movement of directed impact on accuracy of seeding of main technical crops

2020 ◽  
Vol 11 (4) ◽  
pp. 41-47
Author(s):  
P. S. Popyk ◽  
Keyword(s):  
Technological Process ◽  
Agricultural Production ◽  
Experimental Studies ◽  
Resource Conservation ◽  
Design Solution ◽  
Innovative Design ◽  
Constructive Solution ◽  
Grain Flow ◽  
Single Grain

The article presents the results of field experimental studies to establish the effect of the speed of displacement of the metering element on the probability of the appearance of gaps and twins when sowing seeds with a pneumatic-mechanical seeding device equipped with directional cells. The object of the study is a seeding device with a directional metering unit, an innovative design solution of which will improve agricultural production based on resource conservation. As a result of the use of a new constructive solution of the dispenser, the increased accuracy of the technological process of forming a regular single-grain flow of seeds.

scholarly journals Comprehensive Analysis of SRAM Cell Architectures With 18nm FinFET for Low Power Applications

2021 ◽  
Author(s):  
T. Santosh Kumar ◽  
Suman Lata Tripathi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Reduction Technique ◽  
Leakage Currents ◽  
Leakage Reduction ◽  
Sram Cell ◽  
Supply Voltage Scaling ◽  
Better Than

Abstract The SRAM cells are used in many applications where power consumption will be the main constraint. The Conventional 6T SRAM cell has reduced stability and more power consumption when technology is scaled resulting in supply voltage scaling, so other alternative SRAM cells from 7T to 12T have been proposed which can address these problems. Here a low power 7T SRAM cell is suggested which has low power consumption and condensed leakage currents and power dissipation. The projected design has a leakage power of 5.31nW and leakage current of 7.58nA which is 84.9% less than the 7T SRAM cell without using the proposed leakage reduction technique and it is 22.4% better than 6T SRAM and 22.1% better than 8T SRAM cell when both use the same leakage reduction technique. The cell area of the 7T SRAM cell is 1.25µM2, 6T SRAM is 1.079µM2 and that of 8T SRAM is 1.28µM2all the results are simulated in cadence virtuoso using 18nm technology.

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