scholarly journals Design and Analysis of Heterojunction Tunneling Transistor (HETT) based Standard 6T SRAM Cell

2018 ◽  
Vol 7 (3.29) ◽  
pp. 8
Author(s):  
B. V. V. Satyanarayana ◽  
M. Durga Prakash
Keyword(s):  
Low Voltage ◽  
Performance Characteristics ◽  
Subthreshold Swing ◽  
Ultra Low Power ◽  
Design And Implementation ◽  
Low Voltage Operation ◽  
Capacitance Effect ◽  
Sram Cell ◽  
Characteristics Analysis ◽  
Beyond Cmos

Subthreshold Swing (SS) of MOSFETs, which determines the low voltage operation of portable mobile devices, cannot reduce below 60mV/dec that restricts MOSFETs for ultra-low power applications. This work presents design and implementation of high ON current, improved Miller capacitance and reduced Subthreshold Swing heterojunction tunneling transistors (HETTs) for portable electronic systems. The performance of HETT with MOSFET has been compared. In this work, the overlapping of gate/oxide on to source can increase the band to band tunneling (BTBT) and improves the ON current of the transistor. Miller capacitance effect can be reduced by the use of low band offset materials and low energy states of materials like Ge or SiGe. This, in turn, results in better performance characteristics for the transistor.The Proposed design and implementation of HETT include both N-type HETT (NHETT) and P-type HETT (PHETT) fabrications and the performance characteristics analysis of both NHETT and PHETT are provided. The advantages and limitations of both NHETT and PHETT for beyond CMOS technologies, in addition to the basic and structural differences between HETTs and conventional MOSFETs to facilitate the use of HETT in place of MOSFET have been elaborated in detail. The construction process of HETT is not at all completely different which is suitable to MOS Design process and is applicable for portable mobile applications. The power analysis of HETT based standard 6T SRAM cell is provided and the performance is verified with the conventional MOSFET based 6T SRAM cell.  

A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

2013 ◽  
Vol 373-375 ◽  
pp. 1607-1611
Author(s):  
Hong Gang Zhou ◽  
Shou Biao Tan ◽  
Qiang Song ◽  
Chun Yu Peng
Keyword(s):  
Error Correction ◽  
Low Voltage ◽  
Cmos Technology ◽  
Soft Error ◽  
Error Correction Codes ◽  
Cell Design ◽  
Low Voltage Operation ◽  
Sram Cell ◽  
Simulation Results ◽  
Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

scholarly journals Design, Implementation and Power Analysis of Low Voltage Heterojunction Tunnel Field Effect Transistor based Basic 6T SRAM Cell

2019 ◽  
Vol 8 (11) ◽  
pp. 2898-2903 ◽  
Keyword(s):  
Low Voltage ◽  
Electronic Device ◽  
Average Power ◽  
Cmos Technology ◽  
Subthreshold Swing ◽  
Semiconductor Memory ◽  
Energy Applications ◽  
Sram Cell ◽  
Memory Applications ◽  
Mobile Electronic Device

The battery-powered mobile devices limited energy process by MOSFET's due to subthreshold swing and underneath 60mV/dec for ultra fewer energy applications. This research introduces the layout and execution of a mobile electronic device full-on-presence, extended Miller potential, and reduced HETT subthreshold swing effectiveness has been compared with MOSFET's Gate oxide blending on source can increase channel tunneling in this work. To enhance transistor line, Miller capacitance impact can be decreased by using low band offset equipment and small power product of metals such as Ge or SiGe. This, in turn, leads to stronger transistor efficiency features. The proposed layout and execution of HETT includes manufacturing of mutually NHETT and PHETT and efficiency analyzes of both NHETT and PHETT. Concerning the fundamental and skeletal distinctions among MOSFET and HETT to promote the utilization of MOSFET instead of HETT, the benefits and constraints of both NHETT and PHETT have been detailed. HETT's construction process is by no means entirely different, suitable for the scheme of MOS method and suitable for transportable motorized applications. HETT provides the 6T SRAM cell electricity evaluation and the output was reviewed using standard SRAM cell. The average power, maximum power and minimum power of SRAM by using both MOSFET and HETT are obtained and compared. The mask layers of HETT fabrication is not that much difference than MOSFET and hence CMOS MOSFET fabrication is friendly to HETT fabrication. In future, the combination of both CMOS MOSFET and HETT are used, CMOS technology for digital logic and HETT for semiconductor memory applications.

Improvement of Cell Stability at Low Voltage Operation on 6T-SRAM Cell with 0.1μm Channel Width

2005 ◽  
Author(s):  
Hyuck-chai Jung ◽  
Sungsik An ◽  
Yangsoo Son ◽  
Yeongil Cho ◽  
Jeongseok Nam ◽  
...  
Keyword(s):  
Low Voltage ◽  
Channel Width ◽  
Low Voltage Operation ◽  
Sram Cell ◽  
Cell Stability

scholarly journals Ultra Low Power Bandgap Strom- und Spannungsquellen in CMOS-Technologie für integrierte drahtlose Systeme

2006 ◽  
Vol 4 ◽  
pp. 213-217
Author(s):  
T. Fedtschenko ◽  
R. Kokozinski ◽  
S. Kolnsberg
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Ultra Low Power ◽  
Low Voltage Operation

Abstract. In modernen drahtlosen Systemen sind niedriger Stromverbrauch und das Betreiben bei niedriger Spannung (Low Voltage Operation) von entscheidender Bedeutung. Dabei ist für viele elektronische Anwendungen eine genaue Spannungs- bzw. Stromreferenz notwendig. Aus diesem Grund werden an eine Referenzquelle hohe Anforderungen bezüglich ihrer Temperatur- und Langzeitstabilität gestellt, was gleichzeitig schwierig mit den "Low-Power" Anforderungen zu vereinbaren ist. Besonders für die auf passiven Transpondern basierenden RFID-Systeme, bei denen die Energieversorgung der Schaltung aus dem Hochfrequenzträgersignal gewonnen wird, stellt die Erzeugung einer genauen Spannungsreferenz ein Problem dar. Vor allem die Spannungsstabilität und die Unabhängigkeit von Temperatur- und Prozessschwankungen bereiten große Schwierigkeiten. In diesem Artikel wird das Design einer CMOS Bandgap Strom- und Spannungsreferenz, realisiert in einer 0,25 μm CMOS-Prozess-Technologie, mit 2,5 V Versorgungsspannung vorgestellt. Die entwickelte Schaltung hat eine Stromaufnahme von 50 μA bei einer Genauigkeit von 1% im Temperaturbereich von –40°C bis 125°C. Ein Testchip wurde in die Fertigung eingespeist. Ausgehend von einem Überblick über bekannte Realisierungen von Bandgap-Schaltungen wird die Besonderheit der neu entwickelten Low-Power Schaltung vergleichend gegenübergestellt.

scholarly journals Low voltage high speed 8T SRAM cell for ultra-low power applications

2018 ◽  
Vol 7 (3.29) ◽  
pp. 70
Author(s):  
A S. S. Trinadh Kumar ◽  
B V. V. Satyanarayana
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Total Power ◽  
Portable Devices ◽  
Threshold Region ◽  
Ultra Low Power ◽  
Read Operation ◽  
Sram Cell ◽  
Total Power Consumption

The usage of portable devices increasing rapidly in the modern life has led us to focus our attention to increase the performance of the SRAM circuits, especially for low power applications. Basically in six-Transistor (6T) SRAM cell either read or write operation can be performed at a time whereas, in 7T SRAM cell using single ended write operation and single ended read operation both write and read operations will be accomplished simultaneously at a time respectively. When it comes to operate in sub threshold region, single ended read operation will be degraded severely and single ended write operation will be severely degraded in terms of write-ability at lower voltages. To encounter these complications, an eight transistor SRAM cell is proposed. It performs single ended read operation and single ended write operation together even at sub threshold region down to 0.1V with improved read-ability using read assist and improved dynamic write-ability which helps in reducing the consumption of power by attaining a lower data retention voltage point. To reduce the total power consumption in the circuits, two extra access transistors are used in 8T SRAM cell which also helps in reducing the overall delay.  

The Design of Ultra Low Power RF CMOS LNA in Nanometer Technology

2016 ◽  
pp. 229-251
Author(s):  
Kavyashree P. ◽  
Siva S. Yellampalli
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Low Voltage Operation ◽  
Common Gate ◽  
Low Power Cmos ◽  
Power Application

In this chapter, an ultra low power CMOS Common Gate LNA (CGLNA) with a Capacitive Cross-Coupled (CCC) gm boosting scheme is designed and analysed. The technique described has been employed in literature to reduce the Noise Figure (NF) and power dissipation. In this work we have extended the concept for low voltage operation along with improving NF and also for significant reduction in current consumption. A gm boosted CCC-CGLNA is implemented in 90nm CMOS technology. It has a gain of 9.9dB and a noise figure of 0.87dB at 2.4GHz ISM band and consumes less power (0.5mw) from 0.6V supply voltage. The designed gm boosted CCC-CGLNA is suitable for low power application in CMOS technologies.

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