Design, Implementation and Power Analysis of Low Voltage Heterojunction Tunnel Field Effect Transistor based Basic 6T SRAM Cell

The battery-powered mobile devices limited energy process by MOSFET's due to subthreshold swing and underneath 60mV/dec for ultra fewer energy applications. This research introduces the layout and execution of a mobile electronic device full-on-presence, extended Miller potential, and reduced HETT subthreshold swing effectiveness has been compared with MOSFET's Gate oxide blending on source can increase channel tunneling in this work. To enhance transistor line, Miller capacitance impact can be decreased by using low band offset equipment and small power product of metals such as Ge or SiGe. This, in turn, leads to stronger transistor efficiency features. The proposed layout and execution of HETT includes manufacturing of mutually NHETT and PHETT and efficiency analyzes of both NHETT and PHETT. Concerning the fundamental and skeletal distinctions among MOSFET and HETT to promote the utilization of MOSFET instead of HETT, the benefits and constraints of both NHETT and PHETT have been detailed. HETT's construction process is by no means entirely different, suitable for the scheme of MOS method and suitable for transportable motorized applications. HETT provides the 6T SRAM cell electricity evaluation and the output was reviewed using standard SRAM cell. The average power, maximum power and minimum power of SRAM by using both MOSFET and HETT are obtained and compared. The mask layers of HETT fabrication is not that much difference than MOSFET and hence CMOS MOSFET fabrication is friendly to HETT fabrication. In future, the combination of both CMOS MOSFET and HETT are used, CMOS technology for digital logic and HETT for semiconductor memory applications.

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A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.373-375.1607 ◽

2013 ◽

Vol 373-375 ◽

pp. 1607-1611

Author(s):

Hong Gang Zhou ◽

Shou Biao Tan ◽

Qiang Song ◽

Chun Yu Peng

Keyword(s):

Error Correction ◽

Low Voltage ◽

Cmos Technology ◽

Soft Error ◽

Error Correction Codes ◽

Cell Design ◽

Low Voltage Operation ◽

Sram Cell ◽

Simulation Results ◽

Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

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Low-Power High-Speed Double Gate 1-bit Full Adder Cell

International Journal of Electronics and Telecommunications ◽

10.1515/eletel-2016-0045 ◽

2016 ◽

Vol 62 (4) ◽

pp. 329-334 ◽

Cited By ~ 1

Author(s):

Raushan Kumar ◽

Sahadev Roy ◽

C.T. Bhunia

Keyword(s):

Power Consumption ◽

High Speed ◽

Low Voltage ◽

Supply Voltage ◽

Average Power ◽

Full Adder ◽

Cmos Technology ◽

Spice Simulation ◽

Pass Transistor ◽

Voltage Swing

Abstract In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit is able to operate at very low voltage and maintain the proper output voltage swing and also balance the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology. In the proposed technique the most time-consuming and power consuming XOR gates and multiplexer are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94μW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using the SPICE simulation tool at desired broad frequency range. It is also observed that the proposed design may be successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.

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Low Voltage 7T SRAM cell in 32nm CMOS Technology Node

2018 International Conference on Computing, Power and Communication Technologies (GUCON) ◽

10.1109/gucon.2018.8675024 ◽

2018 ◽

Cited By ~ 1

Author(s):

Bhawna Rawat ◽

Kirti Gupta ◽

Nidhi Goel

Keyword(s):

Low Voltage ◽

Cmos Technology ◽

Technology Node ◽

Sram Cell

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Energy optimization of 6T SRAM cell using low-voltage and high-performance inverter structures

International Journal of Electrical and Computer Engineering (IJECE) ◽

10.11591/ijece.v9i3.pp1606-1619 ◽

2019 ◽

Vol 9 (3) ◽

pp. 1606

Author(s):

M. Madhusudhan Reddy ◽

M. Sailaja ◽

K. Babulu

Keyword(s):

Low Voltage ◽

Supply Voltage ◽

Voltage Divider ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Nand Gate ◽

Dynamic Power ◽

Sram Cell ◽

Cell Stability ◽

Static Noise

The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.

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Design and Analysis of Heterojunction Tunneling Transistor (HETT) based Standard 6T SRAM Cell

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i3.29.18450 ◽

2018 ◽

Vol 7 (3.29) ◽

pp. 8

Author(s):

B. V. V. Satyanarayana ◽

M. Durga Prakash

Keyword(s):

Low Voltage ◽

Performance Characteristics ◽

Subthreshold Swing ◽

Ultra Low Power ◽

Design And Implementation ◽

Low Voltage Operation ◽

Capacitance Effect ◽

Sram Cell ◽

Characteristics Analysis ◽

Beyond Cmos

Subthreshold Swing (SS) of MOSFETs, which determines the low voltage operation of portable mobile devices, cannot reduce below 60mV/dec that restricts MOSFETs for ultra-low power applications. This work presents design and implementation of high ON current, improved Miller capacitance and reduced Subthreshold Swing heterojunction tunneling transistors (HETTs) for portable electronic systems. The performance of HETT with MOSFET has been compared. In this work, the overlapping of gate/oxide on to source can increase the band to band tunneling (BTBT) and improves the ON current of the transistor. Miller capacitance effect can be reduced by the use of low band offset materials and low energy states of materials like Ge or SiGe. This, in turn, results in better performance characteristics for the transistor.The Proposed design and implementation of HETT include both N-type HETT (NHETT) and P-type HETT (PHETT) fabrications and the performance characteristics analysis of both NHETT and PHETT are provided. The advantages and limitations of both NHETT and PHETT for beyond CMOS technologies, in addition to the basic and structural differences between HETTs and conventional MOSFETs to facilitate the use of HETT in place of MOSFET have been elaborated in detail. The construction process of HETT is not at all completely different which is suitable to MOS Design process and is applicable for portable mobile applications. The power analysis of HETT based standard 6T SRAM cell is provided and the performance is verified with the conventional MOSFET based 6T SRAM cell.

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Analysis of 6T SRAM Cell in Different Technologies

Circulation in Computer Science ◽

10.22632/ccs-2017-mcsp026 ◽

2017 ◽

Vol MCSP2017 (01) ◽

pp. 7-10 ◽

Cited By ~ 2

Author(s):

Subhashree Rath ◽

Siba Kumar Panda

Keyword(s):

Low Power ◽

Data Storage ◽

Low Voltage ◽

Random Access ◽

Storage Device ◽

Cmos Process ◽

Process Technology ◽

Digital Devices ◽

Noise Margin ◽

Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽

10.3390/electronics10050563 ◽

2021 ◽

Vol 10 (5) ◽

pp. 563

Author(s):

Jorge Pérez-Bailón ◽

Belén Calvo ◽

Nicolás Medrano

Keyword(s):

Power Consumption ◽

Dynamic Range ◽

Low Voltage ◽

Cutoff Frequency ◽

Cmos Technology ◽

Active Area ◽

Current Steering ◽

Low Pass ◽

On Chip ◽

Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

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Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea11010006 ◽

2021 ◽

Vol 11 (1) ◽

pp. 6

Author(s):

Orazio Aiello

Keyword(s):

Integrated Circuits ◽

Electromagnetic Interference ◽

Low Voltage ◽

Current Source ◽

Building Blocks ◽

Cmos Technology ◽

Threshold Region ◽

Output Current ◽

Current Generator ◽

Technology Process

The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions.

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Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽

10.3390/mi12050551 ◽

2021 ◽

Vol 12 (5) ◽

pp. 551

Author(s):

Zhongjian Bian ◽

Xiaofeng Hong ◽

Yanan Guo ◽

Lirida Naviner ◽

Wei Ge ◽

...

Keyword(s):

Nonvolatile Memory ◽

High Speed ◽

Low Voltage ◽

Supply Voltage ◽

Random Access ◽

Magnetic Tunnel Junction ◽

Complementary Metal Oxide Semiconductor ◽

Current Mode ◽

Cmos Technology ◽

Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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