scholarly journals Design for Stuck-at Fault Testability in MCT based Reversible Circuits

2018 ◽  
Vol 68 (4) ◽  
pp. 381 ◽  
Author(s):  
Hari Mohan Gaur ◽  
Ashutosh Kumar Singh ◽  
Umesh Ghaneka
Keyword(s):  
Power Consumption ◽  
Design For Testability ◽  
Logic Circuits ◽  
Operating Costs ◽  
Test Vector ◽  
Test Set ◽  
Reversible Circuits ◽  
General Test ◽  
Large Increment ◽  
Test Vectors

Testability leads to a large increment in operating costs from their original circuits which drastically increases the power consumption in logic circuits. This paper presents a new design for testability methodology for the detection of stuck-at faults in multiple controlled Toffoli based reversible circuits. The circuit is modified in such a manner that the applied test vector reaches all the levels without any change in values on the wires of the circuit. An (n+1) dimensional general test set containing only two test vectors is presented, which provide full coverage of single and multiple stuck-at faults in the circuit. The work is further extended to locate the occurrence of stuck-at faults in the circuit. Deterministic approaches are described and the modification methodology is experimented on a set of benchmarks. The present work achieved a reduction up to $50.58\%$ in operating costs as compared to the existing work implemented on the same platform.

scholarly journals Adjustable PRPG for Low Power Test Patterns

2021 ◽  
Vol 9 (6) ◽  
pp. 195-201
Author(s):  
Nadimulla B. ◽  
Aruna Mastani, S.
Keyword(s):  
Power Consumption ◽  
Binary Sequences ◽  
Testing Time ◽  
Test Vector ◽  
Power Test ◽  
Low Power Test ◽  
Simulation Results ◽  
Self Test ◽  
Set Compression ◽  
Test Vectors

As the power consumption is more in the processes of testing, test vector set compression and controlling of toggling plays a crucial role in reducing the power consumption during test mode. In exploring the controlling techniques of toggling, Pre-Selected Toggling (PRESTO) of test patterns is a technique that can control the toggling of a test patterns in a precise manner in Built-in Self -Test (BIST) architectures. In this paper we modify the architecture of existing Full Version PRESTO that can be used to generate test vectors and in addition binary sequences used as scan chins such that the controlling of sequence of test vectors depends on number of 1’s present in the switch code which is user defined thus reducing the testing time with significant fault coverage, and in addition the optimization is also observed in area and power. The area has decreased by 12.2% and power consumption by 15.43%. The Synthesis and implementation of the architectures are done using Artix7 (xc7a100tcsg324-3) FPGA family. The simulation results have been analyzed through Mentor-graphics Questa-sim 10.7C

Small Test Set Generation with High Diagnosability

2016 ◽  
Vol 25 (04) ◽  
pp. 1650024 ◽  
Author(s):  
Anupam Bhar ◽  
Santanu Chattopadhyay ◽  
Indranil Sengupta ◽  
Rohit Kapur
Keyword(s):  
Fault Detection ◽  
Recent Work ◽  
Diagnostic Test ◽  
Lower Order ◽  
Fault Model ◽  
Test Vector ◽  
Test Set ◽  
Trade Off ◽  
Small Test ◽  
Test Vectors

Between fault detection and diagnostic test, there are many tests with varying degrees of diagnosability. There is trade-off between diagnosability of the test and its length. High diagnosability test is longer and takes more time. In this work, we tried to balance both by generating test slightly longer than normal detection test but with high diagnosability, without affecting fault coverage. The order of test vector application to attain more fault and diagnostic coverage in fewer test patterns is also mentioned. If more diagnosability is required, test vectors till the lower order should be used, whereas shorter test compromises on diagnosability. Our results show similar distinguishing capability as compared with a recent work but with 90% reduction in normalized time. The fault model used in this work is stuck-at fault model.

scholarly journals A Secure Architecture of Design for Testability Structures

2019 ◽  
Vol 8 (2) ◽  
pp. 2816-2820
Keyword(s):  
Design For Testability ◽  
Shift Register ◽  
Linear Feedback Shift Register ◽  
Linear Feedback ◽  
Test Vector ◽  
Area Overhead ◽  
Feedback Shift Register ◽  
Test Vectors ◽  
Reduction In Area ◽  
Secure Architecture

The structures of Scan-based Design for Testability are extremely susceptible towards unapproved access of the signals present inside the chip. This paper suggests a protected output based plan which averts the unapproved access without any compromise in the testability. A unique key for each test vector is provided in the proposed secure architecture. These inimitable keys are produced by a multi-polynomial linear feedback shift register (LFSR) in addition they are utilized as test vectors. The dimensions of the multi polynomial LFSR bit is saved bigger than the dimension of key so as to augment the level of security to the key. As the keys are concealed within the test vectors, there is reduction in area overhead. The amount of security is improved predominantly by changing the key for all test vectors, along with the location of the bit in the test vector by choosing a valid combination out of available test vector generated by multi polynomial LFSR.

BIST-Based Low Power Test Vector Generator and Minimizing Bulkiness of VLSI Architecture

2018 ◽  
Vol 27 (05) ◽  
pp. 1850078 ◽  
Author(s):  
J. Praveen ◽  
M. N. Shanmukha Swamy
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Vlsi Architecture ◽  
Fault Coverage ◽  
Linear Feedback ◽  
Test Vector ◽  
Test Power ◽  
Chip Area ◽  
Test Vector Generator ◽  
Test Vectors

In several pseudorandom built-in self-test (BIST) circuits, the applied test vectors will be generated by a linear feedback shift register (LFSR). This type of test pattern generator (TPG) may generate some repeated test patterns, which unnecessarily increases the test power without contributing much to the fault coverage. Based on the vast designs of TPG engine, the chip area also increases by contributing for the overall power consumption of the IC. This paper presents an approach called low power — bit complements test vector generation (LP-BCTVG) technique with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. In order to reduce the test power, the LP-BCTVG inserts appropriate intermediate vectors in between consecutive test vectors generated by LFSR circuit. Hence, the application of final output vectors of LP-BCTVG circuit over circuit under test decreases the test power compared with LFSR-based BIST. By complementing the output bits of LP-BCTVG, we can reduce the bulkiness of TPG engine approximately by half. This further contributes to the reduced IC size. The obtained simulation results prove that this technique can reduce the overall test power consumption along with better fault coverage when compared with LFSR-based BIST and other recent methods. Here, the proposed approach has been tested on several ISCAS’85, ISCAS’89 and ITC’99 benchmark circuits.

DFT with Universal Test Set for All Missing Gate Faults in Reversible Circuits

2021 ◽  
Author(s):  
Joyati Mondal ◽  
Dipak Kumar Kole ◽  
Hafizur Rahaman ◽  
Debesh Kumar Das ◽  
Bhargab B. Bhattacharya
Keyword(s):  
Test Set ◽  
Universal Test ◽  
Reversible Circuits

scholarly journals ECL-Based SiC Logic Circuits for Extreme Temperatures

2015 ◽  
Vol 821-823 ◽  
pp. 910-913 ◽  
Author(s):  
Luigia Lanni ◽  
Bengt Gunnar Malm ◽  
Mikael Östling ◽  
Carl Mikael Zetterling
Keyword(s):  
Power Consumption ◽  
Oscillation Frequency ◽  
Digital Circuits ◽  
Supply Voltage ◽  
Logic Circuits ◽  
Ring Oscillator ◽  
Extreme Temperatures ◽  
Temperature Range ◽  
Stable Noise ◽  
Gate Design

Integrated digital circuits, fabricated in a bipolar SiC technology, have been successfully tested up to 600 °C. Operated with-15 V supply voltage from 27 up to 600 °C OR-NOR gates exhibit stable noise margins of about 1 or 1.5 V depending on the gate design, and increasing delay-power consumption product in the range 100 - 200 nJ. In the same temperature range an oscillation frequency of about 1 MHz is also reported for an 11-stage ring oscillator.

scholarly journals Optimal Reduction in the Number of Test Vectors for Soft Processor Cores Implemented in FPGA

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2505
Author(s):  
Mariusz Węgrzyn ◽  
Ernest Jamro ◽  
Agnieszka Dąbrowska-Boruch ◽  
Kazimierz Wiatr
Keyword(s):  
Fault Coverage ◽  
Test Vector ◽  
Single Event Upset ◽  
Fault Models ◽  
Test Program ◽  
Global Test ◽  
Test Vectors ◽  
Processor Cores ◽  
Optimal Reduction ◽  
Selection Of

Testing FPGA-based soft processor cores requires a completely different methodology in comparison to standard processors. The stuck-at fault model is insufficient, as the logic is implemented by lookup tables (LUTs) in FPGA, and this SRAM-based LUT memory is vulnerable to single-event upset (SEU) mainly caused by cosmic radiations. Consequently, in this paper, we used combined SEU-induced and stuck-at fault models to simulate every possible fault. The test program written in an assembler was based on the bijective property. Furthermore, the fault detection matrix was determined, and this matrix describes the detectability of every fault by every test vector. The major novelty of this paper is the optimal reduction in the number of required test vectors in such a way that fault coverage is not reduced. Furthermore, this paper also studied the optimal selection of test vectors when only 95% maximal fault coverage is acceptable; in such a case, only three test vectors are required. Further, local and global test vector selection is also described.

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