Highly Scalable ALD-deposited Hafnium Silicate Gate Stacks for Low Standby Power Applications

2006 ◽  
Vol 917 ◽  
Author(s):  
Johan Swerts ◽  
Wim Deweerd ◽  
Chang-gong Wang ◽  
Yanina Fedorenko ◽  
Annelies Delabie ◽  
...  

AbstractThe electrical performance of hafnium silicate (HfSiOx) gate stacks grown by atomic layer deposition (ALD) has been evaluated in capacitors and transistors. First, scaling potential of HfSiOx layers was studied as function of composition and thickness. It is shown that the equivalent oxide thickness scales down with decreasing layer thickness and increasing Hf-content. The gate leakage (at Vfb-1V), however, is mainly determined by the physical layer thickness. For the same equivalent oxide thickness (EOT) target, the lowest leakage is observed for the layers with the highest Hf-content. Leakage values as low as 1x10-3 A/cm2 for an equivalent oxide thickness of 1.3 nm have been obtained. Second, the thermal stability against crystallization of the ALD HfSiOx has been studied and related to their electrical properties. The thermal stability of HfSiOx decreases with increasing Hf-content that necessitates the use of nitridation. The influence of various annealing conditions on the nitrogen incorporation is also studied. Finally, the effect of HfSiOx composition and postdeposition nitridation is discussed on transistor level. TaN metal gate transistor data indicate that nitridation reduces the gate leakage and that Hf-rich HfSiOx layers show the best scaling potential, i.e., highest performance for the lowest gate leakage.

Hyomen Kagaku ◽  
2012 ◽  
Vol 33 (11) ◽  
pp. 610-615
Author(s):  
Yukinori MORITA ◽  
Shinji MIGITA ◽  
Wataru MIZUBAYASHI ◽  
Hiroyuki OTA

2004 ◽  
Vol 811 ◽  
Author(s):  
Joel Barnett ◽  
N. Moumen ◽  
J. Gutt ◽  
M. Gardner ◽  
C. Huffman ◽  
...  

ABSTRACTWe have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.


2016 ◽  
Vol 2016 ◽  
pp. 1-4 ◽  
Author(s):  
Z. N. Khan ◽  
S. Ahmed ◽  
M. Ali

Focusing on sub-10 nm Silicon CMOS device fabrication technology, we have incorporated ultrathin TiN metal gate electrode in Hafnium Silicate (HfSiO) based metal-oxide capacitors (MOSCAP) with carefully chosen Atomic Layer Deposition (ALD) process parameters. Gate element of the device has undergone a detailed postmetal annealed sequence ranging from 100°C to 1000°C. The applicability of ultrathin TiN on gate electrodes is established through current density versus voltage (J-V), resistance versus temperature (R-T), and permittivity versus temperature analysis. A higher process window starting from 600°C was intentionally chosen to understand the energy efficient behavior expected from ultrathin gate metallization and its unique physical state with shrinking thickness. The device characteristics in form of effective electronic mobility as a function of inverse charge density were also found better than those conventional gate stacks used for EOT scaling.


2018 ◽  
Vol 1 (9) ◽  
pp. 4633-4641 ◽  
Author(s):  
Sabina Spiga ◽  
Francesco Driussi ◽  
Gabriele Congedo ◽  
Claudia Wiemer ◽  
Alessio Lamperti ◽  
...  

2009 ◽  
Vol 12 (5) ◽  
pp. G17 ◽  
Author(s):  
S. Van Elshocht ◽  
C. Adelmann ◽  
P. Lehnen ◽  
S. De Gendt

2003 ◽  
Vol 786 ◽  
Author(s):  
Feliciano Giustino ◽  
Alfredo Pasquarello

ABSTRACTWe investigate the dielectric screening across the Si-SiO2 interface using a first-principle approach. By determining the profile of the microscopic polarization and the effective polarizabilities of SiOn (n = 0,‥4) structural units, we show that the variation of the local screening across the interface relates to the chemical grading. The oxide region near the Si substrate shows the same dielectric permittivity as bulk SiO2 as long as the oxide is locally stoichiometric. The suboxide region carries an enhanced permittivity, with a value intermediate between those corresponding to bulk Si and SiO2. The implications of these findings for the scalability of the equivalent oxide thickness in high-κ gate stacks are discussed.


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