Impact of Post Deposition Annealing on Characteristics of HfxZr1-xO2

2009 ◽  
Vol 1155 ◽  
Author(s):  
Dina Triyoso ◽  
Rama H. Hegde ◽  
Rich Gregory ◽  
Greg S. Spencer ◽  
William Taylor
Keyword(s):  
Laser Annealing ◽  
Void Formation ◽  
High Mobility ◽  
Oxide Thickness ◽  
Post Deposition Annealing ◽  
Low Leakage ◽  
High K ◽  
A Minor ◽  
The Impact ◽  
Post Deposition

AbstractIn this paper the impact of post deposition annealing in various ambient on electrical properties of hafnium zirconate (HfxZr1-xO2) high-k dielectrics is reported. ALD HfxZr1-xO2 films are annealed in a nitrogen and/or oxygen ambient at 500°C to 1000°C. Devices annealed at 500°C in N2 has lower equivalent oxide thickness (EOT) of 10Å without significant increase in gate leakage (Jg), threshold voltage (Vt) and only a slight decrease in transconductance (Gm) values compared to 500°C O2 annealed devices. Furthermore, the impact of annealing HfxZr1-xO2 films in a reducing ambient (NH3) is studied. Optimized NH3 anneal on HfxZr1-xO2 results in lower CET, improved PBTI, low sub-threshold swing values, comparable high-field Gm with only a minor degradation in peak Gm compared to control HfxZr1-xO2. Finally, the impact of laser annealing vs. RTP annealed HfxZr1-xO2 films are reported. Laser annealing helped further stabilize tetragonal phase of HfxZr1-xO2 without inducing void formation. Good devices with low leakage, low EOT and high mobility are obtained for laser annealed HfxZr1-xO2.

Electrical Characteristics of Crystalline Gd2O3 Film on Si (111): Impacts of Growth Temperature and Post Deposition Annealing

2010 ◽  
Vol 1252 ◽  
Author(s):  
Gang Niu ◽  
Bertrand Vilquin ◽  
Nicolas Baboux ◽  
Guillaume Saint-Girons ◽  
Carole Plossu ◽  
...  
Keyword(s):  
Molecular Beam ◽  
Defect Density ◽  
Oxide Thickness ◽  
Electrical Characteristics ◽  
Equivalent Oxide Thickness ◽  
Optimal Temperature ◽  
Post Deposition Annealing ◽  
High K ◽  
Electrical Characterizations ◽  
Post Deposition

AbstractThis work reports on the epitaxial growth of crystalline high-k Gd2O3 on Si (111) by Molecular Beam Epitaxy (MBE) for CMOS gate application. Epitaxial Gd2O3 films of different thicknesses have been deposited on Si (111) between 650°C~750°C. Electrical characterizations reveal that the sample grown at the optimal temperature (700°C) presents an equivalent oxide thickness (EOT) of 0.73nm with a leakage current density of 3.6×10-2 A/cm2 at |Vg-VFB|=1V. Different Post deposition Annealing (PDA) treatments have been performed for the samples grown under optimal condition. The Gd2O3 films exhibit good stability and the PDA process can effectively reduce the defect density in the oxide layer, which results in higher performances of the Gd2O3/Si (111) capacitor.

Reduction of CV Hysteresis in Metal/High-k MISFETs Using Flash Lamp Post Deposition Annealing

2004 ◽  
Vol 811 ◽  
Author(s):  
Takeo Matsuki ◽  
Yasushi Akasaka ◽  
Kiyoshi Hayashi ◽  
Masataka Noguchi ◽  
Koji Yamashita ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Gate Insulator ◽  
Flash Lamp ◽  
Gate Electrode ◽  
Post Deposition Annealing ◽  
Hysteresis Width ◽  
High K ◽  
Mis Capacitors ◽  
Hysteresis Characteristics ◽  
Post Deposition

ABSTRACTA Xe flash lamp (FL) heating technique was applied to the post deposition annealing process (PDA) for HfAlOx/SiO2 gate insulator with poly-Si or W/TiN gate electrode in a gate last based process. In the case of W/TiN/HfAlOx/SiO2, CV hysteresis with less than 10mV was achieved using the FL-PDA. However, the FL-PDA increased hysteresis width up to over 100 mV when poly-Si was used as a gate electrode. That occurred also with low temperature (700 °C) rapid thermal PDA process. The lower thermal budget achieved by the flash lamp annealing and the metal gate is effective to suppress the interfacial reaction which causes the traps responsible for the hysteresis. Charge trapping in the W/TiN/HfAlOx/SiO2 was evaluated using CV hysteresis characteristics in the MISFETs and the MIS capacitors. Electron was major trapped charge of the HfAlOx.

Improvement in Contact Resistivity to thin film Bi2Te3

2010 ◽  
Vol 1267 ◽  
Author(s):  
Rahul P Gupta ◽  
Ka Xiong ◽  
John B White ◽  
Kyeongjae Cho ◽  
Bruce Gnade
Keyword(s):  
Thin Film ◽  
Contact Resistance ◽  
Surface Preparation ◽  
Contact Resistivity ◽  
Post Deposition Annealing ◽  
Contact Metallization ◽  
Potential Contact ◽  
Te Material ◽  
The Impact ◽  
Post Deposition

AbstractA study of the impact of surface preparation and post-deposition annealing on contact resistivity for sputtered Ni and Co contacts to thin film Bi2Te3 is presented. The contact resistance values obtained using the transfer length method (TLM) for Ni is compared to Co as a potential contact metal to Bi2Te3. Post-deposition annealing at 100°C on samples that were sputter cleaned reduces the contact resistivity to < 10-7 Ω-cm2 for both Ni and Co contacts to Bi2Te3. Co provided similar contact resistance values as Ni, but had better adhesion and less diffusion into the thermoelectric (TE) material, making it a suitable candidate for contact metallization to Bi2Te3 based devices.

Improvement of TDDB reliability, characteristics of HfO2 high-k/metal gate MOSFET device with oxygen post deposition annealing

2010 ◽  
Vol 50 (5) ◽  
pp. 618-621 ◽  
Author(s):  
Chia-Wei Hsu ◽  
Yean-Kuen Fang ◽  
Wen-Kuan Yeh ◽  
Chun-Yu Chen ◽  
Yen-Ting Chiang ◽  
...  
Keyword(s):  
Metal Gate ◽  
Post Deposition Annealing ◽  
Reliability Characteristics ◽  
High K ◽  
Post Deposition

Stabilization of a very high-k crystalline ZrO2 phase by post deposition annealing of atomic layer deposited ZrO2/La2O3 dielectrics on germanium

2010 ◽  
Vol 256 (16) ◽  
pp. 5031-5034 ◽  
Author(s):  
S. Abermann ◽  
C. Henkel ◽  
O. Bethge ◽  
G. Pozzovivo ◽  
P. Klang ◽  
...  
Keyword(s):  
Atomic Layer ◽  
Post Deposition Annealing ◽  
Zro2 Phase ◽  
High K ◽  
Very High ◽  
Post Deposition

scholarly journals Analog Performance of SOI nMuGFETs with Different TiN Gate Electrode Thickness and High-k Dielectrics

2011 ◽  
Vol 6 (2) ◽  
pp. 102-106
Author(s):  
Milene Galeti ◽  
Michele Rodrigues ◽  
Nadine Collaert ◽  
Eddy Simoen ◽  
Cor Claeys ◽  
...  
Keyword(s):  
Oxide Thickness ◽  
Voltage Gain ◽  
Gate Electrode ◽  
Metal Gate ◽  
Short Channel ◽  
High K ◽  
Analog Performance ◽  
Tin Metal ◽  
High K Dielectric ◽  
The Impact

This work presents an analysis of the analog performance of SOI MuGFET devices and the impact of different TiN metal gate electrode thickness.Thinner TiN metal gate allows achieving large gain and this effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. This VEA increase suggests an increase of the transversal electrical field for thin TiN metal gate (reduced gate oxide thickness) that is confirmed with the increment of the GIDL current.This impact on the voltage gain is maintained for short channel length.The impact of different gate dielectrics was also studied where high-k dielectric indicated a higher VT due to a VFB variation. Additionally, lower intrinsic voltage gain was observed for hafnium dielectric and this can be related to the lower Early voltage (VEA) present in this devices.

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