Fabrication of High Quality Mos Devices for Application in Hazardous Environments Based on Rtp Gate Dielectrics With in Situ Rtcvd of Polysilicon Gates

1993 ◽  
Vol 303 ◽  
Author(s):  
B. Fröschle ◽  
H.P. Bruemmer ◽  
W. Lang ◽  
K. Neumeier ◽  
P. Ramm
Keyword(s):  
Threshold Voltage ◽  
Gate Dielectrics ◽  
Chemical Vapor ◽  
Process Variations ◽  
Interface State ◽  
State Density ◽  
Breakdown Field ◽  
Polysilicon Gate ◽  
Radiation Induced

ABSTRACTProcess modules for MOS gate fabrication were developed which can be completed subsequently in one RTP reactor: atmospheric process sequences for gate oxides and oxynitrides as well as low pressure chemical vapor deposition of polysilicon (RTCVD). Prior to the Rapid Thermal Oxidation (RTO), the wafers were treated with a Rapid Thermal Cleaning process (RTC) in H2/Ar ambient. After the desoxidation step the RTO was done in O2/H2/Ar followed by an anneal (RTA) for the gate oxide or a nitridation in NH3 (RTN) and reoxidation for the oxynitrides, respectively. The polysilicon gate electrode was fabricated either by RTCVD in situ or in a conventional furnace reactor. The two-step RTCVD process resulted in a very good thickness uniformity for the polysilicon layers of 3% (3mm from the edge). The influence of the process variations on breakdown field, fixed oxide charge, interface state density, flatband voltage, and threshold voltage of the different types of gate dielectrics was investigated. The charges and voltages were determined by LF-HF CV measurements. In order to characterize the radiation tolerance of electronic devices, radiation induced flatband and threshold voltage shifts as well as the build up of interface charges were determined. The irradiation was performed at a Co - 60 gamma source. Breakdown fields in the range of 19 MV/cm, interface state densities of less than 109 eV−2cm−2, and radiation induced threshold voltage shifts below 0.1 V after 1.5 Mrad(Si) were obtained.

Fabrication of High Quality MOS Devices for Application in Hazardous Environments Based on RTP Gate Dielectrics with In Situ RTCVD of Polysilicon Gates

1993 ◽  
Vol 300 ◽  
Author(s):  
B. Fröschle ◽  
H.P. Bruemmer ◽  
W. Lang ◽  
K. Neumeier ◽  
P. Ramm
Keyword(s):  
Threshold Voltage ◽  
Gate Dielectrics ◽  
Chemical Vapor ◽  
Process Variations ◽  
Interface State ◽  
State Density ◽  
Breakdown Field ◽  
Polysilicon Gate ◽  
Radiation Induced

ABSTRACTProcess modules for MOS gate fabrication were developed which can be completed subsequently in one RTP reactor: atmospheric process sequences for gate oxides and oxynitrides as well as low pressure chemical vapor deposition of polysilicon (RTCVD). Prior to the Rapid Thermal Oxidation (RTO), the wafers were treated with a Rapid Thermal Cleaning process (RTC) in H2/Ar ambient. After the desoxidation step the RTO was done in O2/H2/Ar followed by an anneal (RTA) for the gate oxide or a nitridation in NH3 (RTN) and reoxidation for the oxynitrides, respectively. The polysilicon gate electrode was fabricated either by RTCVD in situ or in a conventional furnace reactor. The two-step RTCVD process resulted in a very good thickness uniformity for the polysilicon layers of 3% (3mm from the edge). The influence of the process variations on breakdown field, fixed oxide charge, interface state density, flatband voltage, and threshold voltage of the different types of gate dielectrics was investigated. The charges and voltages were determined by LF-HF CV measurements. In order to characterize the radiation tolerance of electronic devices, radiation induced flatband and threshold voltage shifts as well as the build up of interface charges were determined. The irradiation was performed at a Co - 60 gamma source. Breakdown fields in the range of 19 MV/cm, interface state densities of less than 109 eV−1cm−2, and radiation induced threshold voltage shifts below 0.1 V after 1.5 Mrad(Si) were obtained.

Properties of Thin SiO2 Films with In-Situ Deposition of Poly Si Electrodes

1989 ◽  
Vol 146 ◽  
Author(s):  
Paihung Pan ◽  
Ahmad Kermani ◽  
Wayne Berry ◽  
Jimmy Liao
Keyword(s):  
Electrical Properties ◽  
Breakdown Strength ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
In Situ Deposition ◽  
Different Temperatures ◽  
Flatband Voltage ◽  
Si Films

ABSTRACTElectrical properties of thin (12 nm) SiO2 films with and without in-situ deposited poly Si electrodes have been studied. Thin SiO2 films were grown by the rapid thermal oxidation (RTO) process and the poly Si films were deposited by the rapid thermal chemical vapor deposition (RTCVD) technique at 675°C and 800°C. Good electrical properties were observed for SiO2 films with thin in-situ poly Si deposition; the flatband voltage was ∼ -0.86 V, the interface state density was < 2 × 1010/cm2/eV, and breakdown strength was > 10 MV/cm. The properties of RTCVD poly Si were also studied. The grain size was 10-60 rim before anneal and was 50-120 rim after anneal. Voids were found in thin (< 70 nm) RTCVD poly Si films. No difference in either SiO2 properties or poly Si properties was observed for poly Si films deposited at different temperatures.

Effect of Thermal Stability and Roughness on Electrical Properties of Tantalum Oxide Gates

1999 ◽  
Vol 567 ◽  
Author(s):  
G.B. Alers ◽  
L.A. Stirling ◽  
R.B. Vandover ◽  
J.P. Chang ◽  
D.J. Werder ◽  
...  
Keyword(s):  
High Temperature ◽  
Gate Dielectrics ◽  
Tantalum Oxide ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Effective Dielectric Constant ◽  
Leakage Currents ◽  
Temperature Plasma ◽  
The Impact

ABSTRACTGate dielectrics with an effective SiO2 thickness of 1.6 nm (100 Hz) have been fabricated using chemical vapor deposition of tantalum oxide directly on silicon. A low temperature plasma anneal process was used to passivate excess traps in the oxide layer and to avoid degradation of capacitance and leakage after high temperature processing. Stable capacitance-voltage characteristics were obtained after the plasma anneal with an interface state density of ∼ 1012 cm−2 before post metallization anneal. We have examined the impact of high temperature processes and crystallization on the roughness for 10nm – 50nm films of Ta2O5 films on Si and SiN. The impact of roughness on capacitance and leakage current is examined through calculations assuming a Gaussian distribution of thickness across the capacitor with two conductive contacts. It is found that when the rms roughness exceeds about 20% of the film thickness then an increase in capacitance is observed that can be mistaken as an effective dielectric constant increase. The increase in capacitance due to roughness is accompanied by an exponential increase in leakage currents that ultimately degrades the charge storage capacity of the oxide.

300° C Processing of Si Using Remote Plasma Techniques for In Situ Cleaning, Epitaxy, and Oxide/Nitride/Oxide Depositions

1989 ◽  
Vol 146 ◽  
Author(s):  
G.G. Fountain ◽  
S.V. Hattangady ◽  
R.A. Rudder ◽  
J.B. Posthill ◽  
R.J. Markunas
Keyword(s):  
Past History ◽  
Chemical Vapor ◽  
Deposition Process ◽  
Interface State ◽  
State Density ◽  
Hydrogen Treatment ◽  
Remote Plasma ◽  
Nitride Oxide ◽  
By Products

ABSTRACTLow temperature Si processing techniques have been developed using remote plasma enhanced chemical vapor techniques. The 300° C in situ processes include indirectly excited hydrogen treatments for obtaining reconstructed Si(100) surfaces, Si/Si(100) homoepitaxy, and deposition of poly-Si/oxide/nitride/oxide/Si(100) structures with no capacitance-voltage hysteresis and low interface state density (4×1010cm−2eV−1). While all these processes have been accomplished with the same tool, the success of the in situ hydrogen treatment and the homoepitaxy are sensitive to the past history of the reactor. In particular, they are sensitive to by-products formed during the oxide deposition process. To eliminate these by-products, plasma conditioning of the chamber walls prior to introduction of the silicon wafer from the load lock has been necessary to obtain reproducible results.

High Integrity SiO2/Al2O3 Gate Stack for Normally-off GaN MOSFET

2013 ◽  
Vol 1561 ◽  
Author(s):  
Hiroshi Kambayashi ◽  
Takehiko Nomura ◽  
Hirokazu Ueda ◽  
Katsushige Harada ◽  
Yuichiro Morozumi ◽  
...  
Keyword(s):  
Field Effect ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Gate Insulator ◽  
Oxide Semiconductor ◽  
Breakdown Field ◽  
Mos Transistors ◽  
Gate Stack ◽  
High Integrity

ABSTRACTHigh integrity SiO2/Al2O3 gate stack has been demonstrated for GaN metal-oxide-semiconductor (MOS) transistors. The SiO2 film formed on GaN by the microwave-excited plasma enhanced chemical vapor deposition (MW-PECVD) exhibits good properties compared that by the LP (Low Pressure)-CVD. Then, by incorporating the advantages of both of SiO2 with a high insulating and Al2O3 with good interface characteristics, the SiO2/Al2O3 gate stack structure has been employed in GaN MOS devices. The structure shows a low interface state density between gate insulator and GaN, a high breakdown field, and a large charge-to-breakdown by applying 3-nm Al2O3. The SiO2/Al2O3 gate stack has also been applied to AlGaN/GaN hybrid MOS heterojunction field-effect transistor (HFET) and the HFET shows excellent properties with the threshold voltage of 4.2 V and the maximum field-effect mobility of 192 cm2/Vs.

Identification of Charging Effects in Plasma-Enhanced TEOS Deposition with Non-Contact Test Techniques

1998 ◽  
Author(s):  
Tomasz Brozek ◽  
James Heddleson
Keyword(s):  
Vapor Deposition ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Wafer Surface ◽  
Oxide Charge ◽  
Contact Test ◽  
Deposition Power ◽  
Oxide Deposition

Abstract Use of non-contact test techniques to characterize degradation of the Si-SiO2 system on the wafer surface exposed to a plasma environment have proven themselves to be sensitive and useful in investigation of plasma charging level and uniformity. The current paper describes application of the surface charge analyzer and surface photo-voltage tool to explore process-induced charging occurring during plasma enhanced chemical vapor deposition (PECVD) of TEOS oxide. The oxide charge, the interface state density, and dopant deactivation are studied on blanket oxidized wafers with respect to the effect of oxide deposition, power lift step, and subsequent annealing.

The Properties Of a-Si:H/c-Si Heterostructures Prepared By 55 kHz Pecvd For Solar Cell Application

1997 ◽  
Vol 485 ◽  
Author(s):  
B. G Budaguan ◽  
A. A. Aivazov ◽  
A. A. Sherchenkov ◽  
A. V Blrjukov ◽  
V. D. Chernomordic ◽  
...  
Keyword(s):  
Crystalline Silicon ◽  
Low Frequency ◽  
Reverse Current ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Solar Cell Application ◽  
Current Voltage ◽  
Frequency Plasma ◽  
Device Applications

AbstractIn this work a-Si:H/c-Si heterostructures with good electronic properties of a-Si:H were prepared by 55 kHz Plasma Enhanced Chemical Vapor Deposition (PECVD). Currentvoltage and capacitance-voltage characteristics of a-Si:H/c-Si heterostructures were measuredto investigate the influence of low frequency plasma on the growing film and amorphous silicon/crystalline silicon boundary. It was established that the interface state density is low enough for device applications (<2.1010 cm−2). The current voltage measurements suggest that, when forward biased, space-charge-limited current determines the transport mechanism in a- Si:H/c-Si heterostructures, while reverse current is ascribed to the generation current in a-Si:H and c-Si depletion layers.

Low Interface State Density Oxide-GaAs Structures Fabricated by In-Situ Molecular Beam Epitaxy

1996 ◽  
Vol 421 ◽  
Author(s):  
M. Passlack ◽  
M. Hong
Keyword(s):  
Molecular Beam Epitaxy ◽  
Molecular Beam ◽  
Molecular Beams ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
In Situ Deposition ◽  
Interface Recombination Velocity ◽  
Recombination Velocity

AbstractWe have extended the spectrum of molecular-beam epitaxy (MBE) related techniques by introducing in-situ deposition of oxides. The oxide films have been deposited on clean, atomically ordered (100) GaAs wafer surfaces using molecular beams of gallium-, magnesium-, silicon-, or aluminum oxide. Among the fabricated oxide-GaAs heterostructures, Ga2O3-GaAs interfaces exhibit unique electronic properties including an interface state density Dit in the low 1010 cm−2eV−1 range and an interface recombination velocity S of 4000 cm/s. The formation of inversion layers in both n- and p-type GaAs has been clearly established. Further, thermodynamic and photochemical stability of excellent electronic interface properties of Ga2O3-GaAs structures has been demonstrated.

scholarly journals Oxide Degradation Effects in Dry Patterning of Resist Using Neutral Oxygen Beams

1992 ◽  
Vol 268 ◽  
Author(s):  
Walter E. Mlynko ◽  
Srinandan R. Kasi ◽  
Dennis M. Manos
Keyword(s):  
Dielectric Breakdown ◽  
Electrical Characterization ◽  
Plasma Source ◽  
Interface State ◽  
State Density ◽  
Low Energy ◽  
Carrier Injection ◽  
Polysilicon Gate ◽  
Atomic Beams ◽  
Novel Processing

ABSTRACTNovel processing methods are being studied to address the highly selective and directional etch requirements of the ULSI manufacturing era; neutral molecular and atomic beams are two promising candidates. In this study, the potential of 5 eV neutral atomic oxygen beams for dry development of photoresist is demonstrated for application in patterning of CMOS devices. The patterning of photoresist directly on polysilicon gate layers enables the use of a self-contained dry processing strategy, with oxygen beams for resist etching and chlorine beams for polysilicon etching. Exposure to such reactive low-energy species and to the UV radiation from the line-of-sight, high-density plasma source can, however, alter MOSFET gate oxide quality, impacting device performance and reliability. We have studied this process-related device integrity issue by subjecting polysilicon gate MOS structures to exposure treatments of 5–20 eV oxygen beams similar to those used for resist patterning. Electrical characterization shows a significant increase in the oxide trapped charge (30–90x) and interface state density (30–60x) upon low-energy exposure. Current-voltage(IV) and dielectric breakdown characterization show increased low-field leakage characteristics for the same exposure. High-field electron injection studies reveal that the 0.25–V to 0.5–V negative flatband shifts (measured after oxygen beam exposure) can be partially annealed by carrier injection. This could be due to positive charge annihilation or electron trapping, or some combination of both. SEM and electrical analysis of structures exposed to neutral beam processing are presented along with the results of thermal annealing treatments.

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