Growth of Thin SiO2 bY “SPIKE” Rapid Thermal Oxidation

1999 ◽  
Vol 567 ◽  
Author(s):  
A. T. Fiory

ABSTRACTWafers prepared with HF and RCA cleaning were oxidized at atmospheric pressure O2 with an incandescent-lamp processor using temperature ramping at rates up to 150°C/s for heating and 80°C/s for cooling. The minimum oxidation time obtained by the “spike” method of turning off lamp power prior to reaching a desired peak temperature is effectively 2s. Film thickness for spike oxidation ranges from about 1.6 nm for peak temperature of 1000°C to about 2.2 nm for peak temperature of 1100°C. Activation energies of 2.5 eV are determined for 1.5 – 4 nm films. Films grown for varied times and temperatures to produce equal oxide thickness, as measured by ellipsometry, show nearly equivalent physical properties in measurements by corona-charge and Kelvin probe surface photovoltage techniques.

1997 ◽  
Vol 470 ◽  
Author(s):  
G. C. Xing ◽  
D. Lopes ◽  
G. E. Miner

ABSTRACTIn this paper, we report the study of rapid thermal oxidation of silicon in N2O ambient using the Applied Materials RTP Centura rapid thermal processor, and N2O oxide thickness and compositional uniformities with respect to gas flow rate and wafer rotation speed as well as other process parameters. It was found that N2O oxide uniformity is strongly dependent on gas flow rate and wafer rotation speed in addition to process pressure. With optimized setting of the process parameters, excellent oxidation uniformities (one sigma < 1%) were obtained at atmospheric pressure N2O ambient. Nitrogen concentrations of such uniform oxides grown at 1050°C atmospheric pressure N2O oxidation processes were 1.7% for a 40Å oxide and 2.5% for a 60Å oxide, respectively, as characterized by SIMS analysis.


2003 ◽  
Vol 786 ◽  
Author(s):  
Bert Lägel ◽  
Maria D. Ayala ◽  
Elena Oborina ◽  
Rudy Schlaf

ABSTRACTCorona charge deposition methods in combination with spatially resolved surface potential measurements have become a standard tool for Si oxide quality monitoring. Based on this technique oxide-semiconductor interface parameters such as surface barrier height, oxide thickness and oxide charge density can now be monitored in-line with commercially available devices. The ongoing downscaling of integrated circuits into the sub-100 nm regime makes the development of high resolution oxide screening methods increasingly important.However, currently available commercial devices are limited in their spatial resolution since they employ the traditional vibrating Kelvin probe technique, restricting their lateral resolution to several μm. In order to increase the lateral resolution of this measurement method we have combined the corona-charge deposition technique with Kelvin Probe AFM. We present initial results of this novel measurement technique and demonstrate its feasibility by measurements on lithographically prepared oxide patterns on Si wafers with different oxide thicknesses.


Materials ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 728
Author(s):  
David Donnermeyer ◽  
Magdalena Ibing ◽  
Sebastian Bürklein ◽  
Iris Weber ◽  
Maximilian P. Reitze ◽  
...  

The aim of this study was to gain information about the effect of thermal treatment of calcium silicate-based sealers. BioRoot RCS (BR), Total Fill BC Sealer (TFBC), and Total Fill BC Sealer HiFlow (TFHF) were exposed to thermal treatment at 37 °C, 47 °C, 57 °C, 67 °C, 77 °C, 87 °C and 97 °C for 30 s. Heat treatment at 97 °C was performed for 60 and 180 s to simulate inappropriate application of warm obturation techniques. Thereafter, specimens were cooled to 37 °C and physical properties (setting time/flow/film thickness according to ISO 6876) were evaluated. Chemical properties (Fourier-transform infrared spectroscopy) were assessed after incubation of the specimens in an incubator at 37 °C and 100% humidity for 8 weeks. Statistical analysis of physical properties was performed using the Kruskal-Wallis-Test (P = 0.05). The setting time, flow, and film thickness of TFBC and TFHF were not relevantly influenced by thermal treatment. Setting time of BR decreased slightly when temperature of heat application increased from 37 °C to 77 °C (P < 0.05). Further heat treatment of BR above 77 °C led to an immediate setting. FT-IR spectroscopy did not reveal any chemical changes for either sealers. Thermal treatment did not lead to any substantial chemical changes at all temperature levels, while physical properties of BR were compromised by heating. TFBC and TFHF can be considered suitable for warm obturation techniques.


2021 ◽  
pp. 161130
Author(s):  
Calin Constantin Moise ◽  
Laura-Bianca Enache ◽  
Veronica Anastasoaie ◽  
Oana Andreea Lazar ◽  
Geanina Valentina Mihai ◽  
...  

1991 ◽  
Vol 226 ◽  
Author(s):  
Hideo Miura ◽  
Hiroshi Sakata ◽  
Shinji Sakata Merl

AbstractThe residual stress in silicon substrates after local thermal oxidation is discussed experimentally using microscopic Raman spectroscopy. The stress distribution in the silicon substrate is determined by three main factors: volume expansion of newly grown silicon–dioxide, deflection of the silicon–nitride film used as an oxidation barrier, and mismatch in thermal expansion coefficients between silicon and silicon dioxide.Tensile stress increases with the increase of oxide film thickness near the surface of the silicon substrate under the oxide film without nitride film on it. The tensile stress is sometimes more than 100 MPa. On the other hand, a complicated stress change is observed near the surface of the silicon substrate under the nitride film. The tensile stress increases initially, as it does in the area without nitride film on it. However, it decreases with the increase of oxide film thickness, then the compressive stress increases in the area up to 170 MPa. This stress change is explained by considering the drastic structural change of the oxide film under the nitride film edge during oxidation.


2002 ◽  
Vol 747 ◽  
Author(s):  
Antonio C. Oliver ◽  
Jack M. Blakely

ABSTRACTSurface and interface morphology may play an important role in the electrical performance of metal-oxide-semiconductor (MOS) devices with small characteristic dimensions. In previous work we showed how steps on the silicon surface influence the Si-SiO2 interface morphology and the outer oxide surface morphology following thermal oxidation [1]. The Si-SiO2 interface morphology is largely determined by the starting silicon substrate step distribution and atomic steps at the Si surface cause an inherent variation in oxide thickness after thermal oxidation. In the present study we report how roughness caused by increased interfacial step density may affect the electronic tunneling characteristics of an MOS device structure. To determine the extent to which the step morphology plays a role in the tunneling behavior of such devices, similar arrays of capacitors were fabricated on both Si surfaces with reduced step density and surfaces which had not undergone any special surface step removal treatment. The leakage currents due to tunneling for the two types of capacitors were measured and compared. Atomic steps cause an effective decrease in oxide thickness in those capacitors without reduced step density and this leads to increased leakage current.


Author(s):  
Monika Kwoka ◽  
Michal A. Borysiewicz ◽  
Pawel Tomkiewicz ◽  
Anna Piotrowska ◽  
Jacek Szuber

In this paper a novel type of a highly sensitive gas sensor device based on the surface photovoltage effect is described. The developed surface photovoltage gas sensor is based on a reverse Kelvin probe approach. As the active gas sensing electrode the porous ZnO nanostructured thin films are used deposited by the direct current (DC) reactive magnetron sputtering method exhibiting the nanocoral surface morphology combined with an evident surface nonstoichiometry related to the unintentional surface carbon and water vapor contaminations. Among others, the demonstrated SPV gas sensor device exhibits a high sensitivity of 1 ppm to NO2 with a signal to noise ratio of about 50 and a fast response time of several seconds under the room temperature conditions.


2014 ◽  
Vol 1691 ◽  
Author(s):  
Alexandre Savtchouk ◽  
John D’Amico ◽  
Marshall Wilson ◽  
Jacek Lagowski ◽  
Wei-E Wang ◽  
...  

ABSTRACTWe report the first successful application of corona charging noncontact C-V and I-V metrology to interface and dielectric characterization of high-k/III-V structures. The metrology, which has been commonly used in Si IC manufacturing, uses incremental corona charge dosing, ΔQC, on the dielectric surface, and the measurement of surface voltage response, ΔVS, using a Kelvin-probe. Its application to In0.53Ga0.47As with a high-k stack required modifications related to the effects of dielectric trap induced voltage transients. The developed Corona Charge-Kelvin Probe Metrology adopted strictly differential measurements using ΔQC and ΔV, and corresponding differential capacitance rather than measurements based on total global charge, Q, and voltage, V, values.Electrical characterization data including interface trap density, electrical oxide thickness, and dielectric leakage are presented for a sample containing an In0.53 Ga0.47 As channel overlaid with a bilayer (2nm Al2O3/5nm HfO2) dielectric stack that is considered to be very promising for application in performance NFETs with high-mobility channels.


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