Effect of Ramp Annealing to Ni Induced Lateral Crystallization of Amorphous Silicon

2000 ◽  
Vol 609 ◽  
Author(s):  
S. Shivani ◽  
M.C. Poon ◽  
M. Chan ◽  
P.K. Ko
Keyword(s):  
Grain Size ◽  
Amorphous Silicon ◽  
High Performance ◽  
Low Cost ◽  
New Technology ◽  
Silicon On Insulator ◽  
Effect Of Temperature ◽  
Process Time ◽  
Nickel Metal ◽  
Lateral Crystallization

ABSTRACTNickel Metal-Induced-Lateral-Crystallization (MILC) has been used to enlarge the grain size and improve the quality of (poly-Si) Thin-Film-Transistors (TFTs). However, the MILC temperature is still low and the grain size is still small. The feasibility of forming very large grains (single crystal like) from amorphous silicon (a-Si) by combining MILC with ramp annealing has been studied. It has been found that the grain size after ramp annealing is remarkably enhanced and can reach of the order of several ten's of microns. The velocity of MILC with ramp annealing is faster than that of MILC with isothermal annealing. The grain size becomes maximal at around 625°C/2hrs, and saturates at higher temperatures of 625- 1000°C. The effect of temperature, time and other parameters has also been studied in order to maximize the grain size and quality. MILC with ramp annealing at 625°C can greatly lower the process time and reduce the need of subsequent annealing to enhance the grain size. The new technology can have numerous novel applications such as providing a low cost alternative to form silicon-on-insulator (SOI) substrates and a breakthrough for high performance TFTs and novel multi-layers SOI like devices and circuits.

SOI Formation from Amorphous Silicon by Novel Gain Enhancement Method

1999 ◽  
Vol 587 ◽  
Author(s):  
C.Y. Yuen ◽  
M.C. Poon ◽  
M. Chan ◽  
M. Qin ◽  
W.Y. Chan ◽  
...  
Keyword(s):  
Thin Film Transistors ◽  
Low Cost ◽  
New Technology ◽  
Nickel Metal ◽  
Gain Enhancement ◽  
Enhancement Method ◽  
Good Potential ◽  
Lateral Crystallization ◽  
Novel Applications ◽  
Soi Substrates

AbstractLarge grain (> 10 um) poly-Si film has been formed from nickel Metal Induced Lateral Crystallization (MILC) and subsequent high temperature annealing. The fabricated thin film transistors (TFT) have near SOI performance. The new technology has good potential to provide low cost SOI substrates, multi-layer devices and other novel applications.

Nickel Metal Induced Lateral Crystallization of Patterned Amorphous Silicon Thin Film

2007 ◽  
Vol 561-565 ◽  
pp. 1149-1152 ◽  
Author(s):  
Gou Nakagawa ◽  
Tanemasa Asano
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Wide Area ◽  
Competitive Growth ◽  
Silicon Thin Film ◽  
Nickel Metal ◽  
Growth Area ◽  
Lateral Crystallization ◽  
Si Thin Film ◽  
Pattern Width

Metal-induced lateral crystallization (MILC) of patterned amorphous silicon(a-Si) thin film using Ni as a catalyst has been investigated. Ni-MILC grains are based on the growth of needle-like crystals due to the migration of NiSi2 precipitates, which located at the crystalline front, along the <111> directions. In the case where the needle-like crystallites collided at the a-Si pattern edge, not only “turn” or “branch” of the needle-like crystallites toward one of the possible <111> directions but also the growth along the pattern edge were observed. By limiting the growth area, the competitive growth of dendrite crystals that originated in needle-like crystallites was found to appear. This phenomenon resulted in the orientation alignment of MILC crystals in a wide area. Besides, the grain-filtering of MILC crystals was found to be possible by narrowing the pattern width.

High Performance Hyperspectral Imager for Microimaging

2001 ◽  
Vol 7 (S2) ◽  
pp. 14-15
Author(s):  
Henryk Malak ◽  
Petr Herman ◽  
Wayne Moore ◽  
Jaroslav Vecer
Keyword(s):  
Spectral Range ◽  
High Throughput Screening ◽  
High Performance ◽  
Imaging System ◽  
Low Cost ◽  
New Technology ◽  
Ccd Camera ◽  
Imaging Spectrometer ◽  
Parallel Acquisition ◽  
Spectral Imager

A high performance hyperspectral imager with high light throughput suitable for microscopy and analytical imaging was built and tested. The imager utilizes phenomenon of optical activity. The new technique provides a continuous spectral range of several hundreds of nanometers starting in deep UV. Similar spectral range starting in the near IR is also achievable.A performance of a low cost implementation of the new technology is presented. The imager has a form of a microscope adaptor, which is inserted between the microscope and a low-cost 8-bit CCD camera. The resulting instrument is simple, robust, and highly compact. The imager module is placed in-line to the microscope imaging system and does not introduce observable image aberrations. Advantageously, the imager is transparent to conventional imaging operations, thus with the imager in-place there is no need for reconfiguration of the microscope to switch between conventional and hyperspectral video/digital imaging modes.The presented spectral imager answers the need for a practical, sensitive, compact, and affordable imaging spectrometer. The instrument is well suited for a broad range of applications requiring rapid parallel acquisition of highly resolved concurrent spatial and spectral information such as high throughput screening, biochip analysis, remote sensing or nondestructive semiconductor testing.

Effect Of Nickel In Large Grain Poly-Si Film Formed By Nickel Induced Lateral Crystallization and New Grain Enhancement Method

2000 ◽  
Vol 609 ◽  
Author(s):  
W.Y. Chan ◽  
A.M. Myasnikov ◽  
M.C. Poon ◽  
C.Y. Yuen ◽  
P. G. Han ◽  
...  
Keyword(s):  
Low Cost ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
3 Dimensional ◽  
Enhancement Method ◽  
Novel Method ◽  
Amorphous Si ◽  
Lateral Crystallization ◽  
Novel Applications ◽  
Soi Substrates

ABSTRACTLarge grain poly-silicon film (poly-Si) with high material quality and uniformity can have numerous novel applications such as providing a low cost alternative to form silicon-on-insulator (SOI) substrates and a breakthrough technology to ultra-dense 3-dimensional multi-layer SOI like devices and circuits. Nickel Induced Lateral Crystallization (NILC) of amorphous Si (a-Si) has been studied intensively, yet the grains are still small (∼ 1 μm). Recently, we have reported a novel method by combining NILC and a new annealing (at above 900 °C) to form poly-Si film with very large grains ranging from 10 μm to 100 μm. The film has good quality and the TFTs formed are highly comparable to SOI TFTs. This work further reports the effect of Ni to the new large-grain poly-Si film.

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

Impurities and Grain Size Modeling in Recrystallized Silicon

2008 ◽  
Vol 1066 ◽  
Author(s):  
Valeri V. Kalinin ◽  
Alexandre M. Myasnikov ◽  
Vladislav E. Zyryanov
Keyword(s):  
Grain Size ◽  
Quality Control ◽  
Amorphous Silicon ◽  
Computer Aided Design ◽  
Silicon Film ◽  
Calculated Data ◽  
Computer Aided ◽  
Lateral Crystallization ◽  
Aided Design

ABSTRACTIn our previous publications [1, 2 and 3], spreading resistance probe (SRP) measurements for quality control of metal induced lateral crystallization (MILC) of amorphous silicon (a-Si) were studied, and the mechanism of nickel diffusion was simulated using technology computer-aided design (TCAD) modeling.Now, we continue to present the explanation of experimental results by modeling with the Synopsys TCAD package, whereby models for resistivity vs. grain size in implanted recrystallized silicon layers are implemented and compared with experiments.Findings show that the SRP method can be used for the characterization of the MILC process of amorphous silicon and that a comparison of experimental and calculated data allows both a turn from qualitative to quantitative analysis of recrystallized silicon film and an estimate of grain size. It has been found that grain size depends on location in the MILC region and on the time and temperature of recrystallization.

In situ observation of nickel metal-induced lateral crystallization of amorphous silicon thin films

2002 ◽  
Vol 80 (6) ◽  
pp. 944-946 ◽  
Author(s):  
Mitsutoshi Miyasaka ◽  
Kenji Makihira ◽  
Tanemasa Asano ◽  
Efstathios Polychroniadis ◽  
John Stoemenos
Keyword(s):  
Thin Films ◽  
Amorphous Silicon ◽  
In Situ Observation ◽  
Nickel Metal ◽  
Silicon Thin Films ◽  
Lateral Crystallization

High Quality Poly-Si Film and Transistor Formed by Nickel-Induced- Lateral-Crystallization and Pulsed-Rapid-Thermal-Annealing

2001 ◽  
Vol 685 ◽  
Author(s):  
T.C. Leung ◽  
C.F. Cheng ◽  
M.C. Poon
Keyword(s):  
Low Temperature ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
High Performance ◽  
Low Cost ◽  
Drain Current ◽  
Large Area ◽  
High Quality ◽  
Lateral Crystallization ◽  
Si Films

AbstractNickel Induced Lateral Crystallization (NILC) and Pulsed Rapid Thermal Annealing (PRTA) have been used to study new low temperature and high quality poly-silicon (poly-Si) films and thin film transistors (TFTs). The growth rate of poly-Si films has been found to greatly increase from 0.025μm/minute to 1.07μm/minute, and the drain current and performance of TFTs have increased by around 75%. The new poly-Si technology has good potential to apply in high performance, large area, fast throughput, low cost and even low temperature device applications.

scholarly journals Low-Cost, High-Performance Fiber Optic Fabry–Perot Sensor for Ultrasonic Wave Detection

Sensors ◽  
2019 ◽  
Vol 19 (2) ◽  
pp. 406 ◽  
Author(s):  
Haoyong Li ◽  
Delin Li ◽  
Chaoyu Xiong ◽  
Wenrong Si ◽  
Chenzhao Fu ◽  
...  
Keyword(s):  
High Performance ◽  
Microelectromechanical Systems ◽  
Fiber Optic ◽  
Low Cost ◽  
Experimental Tests ◽  
Silicon On Insulator ◽  
Processing Technology ◽  
Fabry Perot ◽  
High Performance Fiber ◽  
The Cost

This study describes a novel fiber optic extrinsic Fabry–Perot interferometric (EFPI) ultrasonic sensor comprising a low-cost and high-performance silicon diaphragm. A vibrating diaphragm, 5 μm thick, was fabricated by using the Microelectromechanical Systems (MEMS) processing technology on a silicon-on-insulator (SOI) wafer. The Fabry–Perot (FP) cavity length was solely determined during the manufacturing process of the diaphragm by defining a specific stepped hole on the handling layer of the SOI wafer, which made the assembly of the sensor easier. In addition, the use of cheap and commercially available components and MEMS processing technology in the development of the sensing system, limited the cost of the sensor. The experimental tests showed that the minimum detectable ultrasonic pressure was 1.5 mPa/sqrt(Hz) –0.625 mPa/sqrt(Hz) between 20 kHz and 40 kHz. As a result, this sensor has the potential to successfully detect weak ultrasonic signals.

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