Molybdenum as a Gate Electrode for Deep Sub-Micron CMOS Technology

2000 ◽  
Vol 611 ◽  
Author(s):  
Pushkar Ranade ◽  
Yee-Chia Yeo ◽  
Qiang Lu ◽  
Hideki Takeuchi ◽  
Tsu-Jae King ◽  
...  
Keyword(s):  
Work Function ◽  
Elevated Temperatures ◽  
Coefficient Of Thermal Expansion ◽  
Cmos Technology ◽  
Gate Electrode ◽  
Short Channel ◽  
Gate Electrodes ◽  
Channel Effects ◽  
Work Functions ◽  
Gate Resistance

ABSTRACTMolybdenum has several properties that make it attractive as a CMOS gate electrode material. The high melting point (∼2610°C) and low coefficient of thermal expansion (5×10−6/°C, at 20 °C) are well suited to withstand the thermal processing budgets normally encountered in a CMOS fabrication process. Mo is among the most conductive refractory metals and provides a significant reduction in gate resistance as compared with doped polysilicon. Mo is also stable in contact with SiO2 at elevated temperatures. In order to minimize short-channel effects in bulk CMOS devices, the gate electrodes must have work functions that correspond to Ec (NMOS) and Ev (PMOS) in Si. This would normally require the use of two metals with work functions differing by about 1V on the same wafer and introduce complexities associated with selective deposition and/or etching. In this paper, the dependence of the work function of Mo on deposition and annealing conditions is investigated. Preliminary results indicate that the work function of Mo can be varied over the range of 4.0-5.0V by a combination of suitable post-deposition implantation and annealing schemes. Mo is thus a promising candidate to replace polysilicon gates in deep sub-micron CMOS technology. Processing sequences which might allow the work function of Mo to be stabilized on either end of the Si energy band gap are explored.

Molybdenum Gate Electrode Technology For Deep Sub-Micron CMOS Generations

2001 ◽  
Vol 670 ◽  
Author(s):  
Pushkar Ranade ◽  
Ronald Lin ◽  
Qiang Lu ◽  
Yee-Chia Yeo ◽  
Hideki Takeuchi ◽  
...  
Keyword(s):  
Work Function ◽  
Cmos Technology ◽  
Potential Candidate ◽  
Gate Electrode ◽  
Metal Gate Electrodes ◽  
Gate Electrodes ◽  
Dielectric Interfaces ◽  
Nitrogen Ions ◽  
Metal Work ◽  
Gate Work Function

ABSTRACTContinued scaling of CMOS technology beyond the 100 nm technology node will rely on fundamental changes in transistor gate stack materials [1]. Refractory metals and their metallic derivatives are among the only candidates suitable for use as transistor gate electrodes. In earlier publications, Mo has been proposed as a potential candidate for use as a MOSFET gate electrode and the implantation of nitrogen ions into the Mo film has been observed to lower the interfacial work function of Mo [2,3]. This observation indicates the potential application of Mo as a CMOS gate electrode. In this paper, the dependence of the interfacial work function on the nitrogen implant parameters (viz. energy and dose) is discussed. In general, metal work functions at dielectric interfaces depend on the permittivity of the dielectric [3,4,5]. This dependence of the gate work function on dielectric permittivity presents a significant challenge for the integration of metal gate electrodes into future CMOS technology. In light of this, the ability to engineer the Mo gate work function over a relatively large range makes it an attractive candidate for this application.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

Dual Work Function CMOS Gate Technology Based on Metal Interdiffusion

2001 ◽  
Vol 670 ◽  
Author(s):  
Igor Polishchuk ◽  
Pushkar Ranade ◽  
Tsu-Jae King ◽  
Chenming Hu
Keyword(s):  
Gate Dielectric ◽  
New Technology ◽  
Cmos Technology ◽  
Dielectric Surface ◽  
Metal Gate ◽  
Gate Electrodes ◽  
Mos Devices ◽  
Low Threshold ◽  
Work Functions ◽  
Electrical Reliability

ABSTRACTIn this paper we propose a new metal-gate CMOS technology that uses a combination of two metals to achieve a low threshold voltage for both n- and p-MOSFET's. One of the gate electrodes is formed by metal interdiffusion so that no metal has to be etched away from the gate dielectric surface. Consequently, this process does not compromise the integrity and electrical reliability of the gate dielectric. This new technology is demonstrated for the Ti-Ni metal combination that produces gate electrodes with 3.9 eV and 5.3 eV work functions for n-MOS and p-MOS devices respectively.

Work Function Engineering With Linearly Graded Binary Metal Alloy Gate Electrode for Short-Channel SOI MOSFET

2012 ◽  
Vol 11 (3) ◽  
pp. 472-478 ◽  
Author(s):  
Sanjoy Deb ◽  
N. Basanta Singh ◽  
Nurul Islam ◽  
Subir Kumar Sarkar
Keyword(s):  
Work Function ◽  
Metal Alloy ◽  
Gate Electrode ◽  
Short Channel ◽  
Soi Mosfet ◽  
Binary Metal

scholarly journals Analysis of Leakage Reduction Techniques in Independent-Gate DG FinFET SRAM Cell

2013 ◽  
Vol 2013 ◽  
pp. 1-8
Author(s):  
Vandna Sikarwar ◽  
Saurabh Khandelwal ◽  
Shyam Akashe
Keyword(s):  
Research Work ◽  
Random Access ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Short Channel ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
Sram Cell ◽  
Channel Effects ◽  
Independent Gate

Scaling of devices in bulk CMOS technology leads to short-channel effects and increase in leakage. Static random access memory (SRAM) is expected to occupy 90% of the area of SoC. Since leakage becomes the major factor in SRAM cell, it is implemented using FinFET. Further, double-gate FinFET devices became a better choice for deep submicron technologies. With this consideration in our research work, 6T SRAM cell is implemented using independent-gate DG FinFET in which both the opposite sides of gates are controlled independently which provides better scalability to the SRAM cell. The device is implemented using different leakage reduction techniques such as gated-Vdd technique and multithreshold voltage technique to reduce leakage. Therefore, power consumption in the SRAM cell is reduced and provides better performance. Independent-gate FinFET SRAM cell using various leakage reduction techniques has been simulated using Cadence virtuoso tool in 45 nm technology.

Analytical Modeling for Short Channel SOI-MOSFET and to Study its Performance

2011 ◽  
Vol 110-116 ◽  
pp. 5150-5154
Author(s):  
K. Senthil Kumar ◽  
Saptarsi Ghosh ◽  
Anup Sarkar ◽  
S. Bhattacharya ◽  
Subir Kumar Sarkar
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Cmos Technology ◽  
Current Drive ◽  
Silicon On Insulator ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Silicon Bulk ◽  
Channel Effects

With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.

scholarly journals Design of Low Power Less Leakage Quarternary Adder Using CMOS

2021 ◽  
pp. 110-121
Author(s):  
M. Sutha ◽  
Dr. R. Nirmala ◽  
Dr. E. Kamalavathi
Keyword(s):  
Low Power ◽  
Impact Ionization ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Surface Scattering ◽  
Short Channel Effects ◽  
Short Channel ◽  
Mos Devices ◽  
Channel Effects ◽  
Quaternary Adder

In VLSI, design and implementation of circuits with MOS devices and binary logic are quite usual. The Main Objective is to design a low power and minimum leakage Quaternary adder. The VLSI field consists of Multi-valued logic (MVL) such as ternary and Quaternary Logic (QTL). The Failures such as Short Channel Effects (SCE) Impact-ionization and surface scattering are in normalized aspects. The Quaternary radix on MVL (multi-valued logic) monitors and reduces the area. The Quaternary (four-valued) logic converts the quaternary signals and binary signals produced by the by the existing binary circuits. The Proposed is carried out with LTSPICE tool and CMOS technology.

scholarly journals Single-Stage Operational Transconductance Amplifier Design in UTBSOI Technology Based on gm/Id Methodology

2019 ◽  
Vol 23 (2) ◽  
Author(s):  
Rekib Uddin Ahmed ◽  
Eklare Akshay Vijaykumar ◽  
Prabir Saha
Keyword(s):  
Graphical Models ◽  
Cmos Technology ◽  
Single Stage ◽  
Silicon On Insulator ◽  
Short Channel ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Channel Effects ◽  
Performance Specifications ◽  
Amplifier Design

The downscaling of complementary metal-oxidesemiconductor (CMOS) technology is approaching its limits imposed by short-channel effects (SCE), thereby multi-gate MOSFETs have been proposed to extend the scalability. Ultrathin-body silicon-on-insulator (UTBSOI) transistor is one of the dual-gated devices which offers better immunity towards SCEs. In this paper, two designs have been proposed for single-stage operational transconductance amplifiers (OTA) using the CMOS and UTBSOI. The CMOS based OTA (CMOS-OTA) has been designed where sizing (W/L) of the constituting MOSFETs have been evaluated through gm/Id methodology and the same OTA topology has been simulated using UTBSOI (UTBSOI-OTA) considering the same W/L. The DC simulation is carried out over the BSIM3v3 model to store the operating point parameters in the form of graphical models. The mathematical expressions for performance specifications have been applied over the graphical models to evaluate the required W/L. Individual comparisons between the two proposed designs have also been carried out for further applications. Based on simulation results at the schematic level, the UTBSOI-OTA has higher DC gain of 33.26% and lesser power consumption of 2.81% over the CMOS-OTA. Moreover, comparative analysis of performance parameters like DC gain and common-mode rejection ratio (CMRR), have been compared with the best-reported paper so far. In addition to this, the UTBSOI-OTA has been applied to practical integrator circuits for further verification.

An Area and Energy Efficient RAM Cell Design in Quantum Dot Cellular Automata

2019 ◽  
Vol 16 (10) ◽  
pp. 4179-4187
Author(s):  
Amanpreet Sandhu ◽  
Sheifali Gupta
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Quantum Dot Cellular Automata ◽  
Channel Effects

The Conventional Complementary Metal oxide semiconductor (CMOS) technology has been revolutionized from the past few decades. However, the CMOS circuit faces serious constraints like short channel effects, quantum effects, doping fluctuations at the nanoscale which limits them to further scaling down at nano meter range. Among various existing nanotechnologies, Quantum dot Cellular Automata (QCA) provides new solution at nanocircuit design. The technical advancement of the paper lies in designing a high performance RAM cell with less QCA cells, less occupational area and lower power dissipation characteristics. The design occupies 12.5% lower area, 16.6% lower input to output delay, and dissipates 18.26% lesser energy than the designs in the literature. The proposed RAMcell is robust due to lesser noise variations. Also it has less fabrication cost due to absence of rotated cells.

scholarly journals Technology and Modeling of Nonclassical Transistor Devices

2019 ◽  
Vol 2019 ◽  
pp. 1-18
Author(s):  
George V. Angelov ◽  
Dimitar N. Nikolov ◽  
Marin H. Hristov
Keyword(s):  
New Technologies ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Thin Body ◽  
Compact Modeling ◽  
Short Channel ◽  
Strained Si ◽  
Channel Effects ◽  
High Carrier Mobility ◽  
High Carrier

This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

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