scholarly journals Visible-Blind UV Digital Camera Based On a 32 × 32 Array of GaN/AlGaN p-i-n Photodiodes

1999 ◽  
Vol 4 (1) ◽  
Author(s):  
J.D. Brown ◽  
Zhonghai Yu ◽  
J. Matthews ◽  
S. Harney ◽  
J. Boney ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Room Temperature ◽  
Digital Camera ◽  
Frame Rate ◽  
Readout Integrated Circuit ◽  
Type Layer ◽  
New Type ◽  
Photodiode Array ◽  
P Type ◽  
Visible Blind

A visible-blind UV camera based on a 32 × 32 array of backside-illuminated GaN/AlGaN p-i-n photodiodes has been successfully demonstrated. Each of the 1024 photodiodes in the array consists of a base n-type layer of AlGaN (~20%) onto which an undoped GaN layer followed by a p-type GaN layer is deposited by metallorganic vapor phase epitaxy. Double-side polished sapphire wafers are used as transparent substrates. Standard photolithographic, etching, and metallization procedures were employed to obtain fully-processed devices. The photodiode array was hybridized to a silicon readout integrated circuit using In bump bonds. Output from the UV camera was recorded at room temperature at a frame rate of 30 Hz. This new type of visible-blind digital camera is sensitive to radiation from 320 nm to 365 nm in the UV spectral region.

scholarly journals UV-Specific (320-365 nm) Digital Camera Based On a 128×128 Focal Plane Array of GaN/AlGaN p-i-n Photodiodes

2000 ◽  
Vol 5 (1) ◽  
Author(s):  
J.D. Brown ◽  
J. Boney ◽  
J. Matthews ◽  
P. Srinivasan ◽  
J.F. Schetzina ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Room Temperature ◽  
Electrical Contact ◽  
Digital Camera ◽  
Readout Integrated Circuit ◽  
Organic Vapor ◽  
Type Layer ◽  
Metal Organic ◽  
Photodiode Array ◽  
P Type

An ultraviolet-specific (320-365 nm) digital camera based on a 128×128 array of backside-illuminated GaN/AlGaN p-i-n photodiodes has been successfully developed. The diode structure consists of a base n-type layer of AlGaN (~23% Al) followed by undoped and then p-type GaN layers deposited by metal organic vapor phase epitaxy. Double-side polished sapphire wafers serve as transparent substrates. Standard photolithographic, etching, and metallization procedures were employed to fabricate the devices. The fully-processed photodiode array was hybridized to a silicon readout integrated circuit (ROIC) using In bump bonds for electrical contact. The UV camera was operated at room temperature at frame rates ranging from 15 to 240 Hz. A variety of UV scenes were successfully recorded with this configuration.

Investigation of Warpage Behavior of Silicon Semiconductor on a Silicon - Adhesive - Ceramic Integrated Structure at Cryogenic Temperatures--STUDENT BEST PAPER $1500

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001751-001772
Author(s):  
Eyup Can Baloglu ◽  
Tuba Okutucu Ozyurt ◽  
Zafer Dursunkaya
Keyword(s):  
Thermal Cycling ◽  
Silicon Wafer ◽  
Integrated Circuit ◽  
Room Temperature ◽  
Thermal Stresses ◽  
Base Material ◽  
Cryogenic Temperatures ◽  
Readout Integrated Circuit ◽  
Silicon Material ◽  
Integrated Structures

Silicon wafer is widely used as a base material for readout integrated circuit (ROIC) of infrared sensors. There is a heterogeneous component assembly with the silicon wafer material. Warpage behavior of silicon readout integrated circuit is dependent on the material properties and geometrical properties of the integrated materials. Warpage behavior of the silicon material directly affects the warpage of the sensor which must be operated at cryogenic temperatures (around 80 K). There exist a great difference between the operation and storage temperatures (~ 300 K) of these devices. When different materials with different thermal expansion coefficients are used such devices, thermal stresses develop on the components and surface deformations named as “warpage” are observed on the materials. The measurement of excessive thermal stress or warpage formation on the sensor is vital for reliability issues. In this study, warpage behavior of silicon material is examined in the temperature range from room temperature down to cryogenic temperatures (80 K) and under vacuum conditions less than 1 mTorr. The silicon ROIC is integrated on an alumina ceramic by applying an adhesive between these two layers. After the application of the adhesive material, the integration of the silicon to ceramic is accomplished using a pick and place equipment. The warpage of silicon wafer is measured by a Fizeau Laser Interferometer which uses a 633 nanometer wavelength He – Ne laser. The warpage of the diced silicon is measured before and after the integration to the ceramic so that the effect of curing process of the adhesive is determined after which, the warpage of the silicon material is measured at atmospheric pressure and also under vacuum conditions at room temperature. The warpage of silicon material on the integrated structure is measured with increments of 10 K for both cooling from room temperature to 80 K and heating from 80 K to room temperature. In order to reach cryogenic temperatures, a liquid nitrogen cooled vacuum envelope is utilized. The envelope has an optical flat (made of BK7 material and 2.35 mm thick) for interferometric measurements. There are a total of five integrated structures for the warpage measurements. At each of these structures, the silicon material thickness is different. Comparison of the warpage behavior of the silicon material for different thicknesses are performed. Thermal cycling between room temperature and 80 K is also performed up to 5 cycles for each of the integrated structures. Thermal cycling effect on silicon warpage is discussed for silicon - alumina - adhesive trimaterial assembly structure.

ESEM - A multipurpose surface Electron Microscope

1986 ◽  
Vol 44 ◽  
pp. 632-633 ◽  
Author(s):  
G.D. Danilatos
Keyword(s):  
Electron Microscope ◽  
Room Temperature ◽  
Environmental Scanning ◽  
Gas Composition ◽  
Saturated Water Vapor ◽  
Surface Electron ◽  
Current State ◽  
Saturated Water ◽  
New Type ◽  
Temperature And Pressure

Over recent years a new type of electron microscope - the environmental scanning electron microscope (ESEM) - has been developed for the examination of specimen surfaces in the presence of gases. A detailed series of reports on the system has appeared elsewhere. A review summary of the current state and potential of the system is presented here.The gas composition, temperature and pressure can be varied in the specimen chamber of the ESEM. With air, the pressure can be up to one atmosphere (about 1000 mbar). Environments with fully saturated water vapor only at room temperature (20-30 mbar) can be easily maintained whilst liquid water or other solutions, together with uncoated specimens, can be imaged routinely during various applications.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

Dependence of the Deformation of 128×128 InSb Focal-plane Arrays on the Silicon Readout Integrated Circuit Thickness

2015 ◽  
Vol 9 (1) ◽  
pp. 170-174 ◽  
Author(s):  
Xiaoling Zhang ◽  
Qingduan Meng ◽  
Liwen Zhang
Keyword(s):  
Thermal Shock ◽  
Indium Antimonide ◽  
Integrated Circuit ◽  
Focal Plane ◽  
Three Dimensional ◽  
Fracture Probability ◽  
Focal Plane Arrays ◽  
Thermal Shock Test ◽  
Readout Integrated Circuit ◽  
Three Dimensional Modeling

The square checkerboard buckling deformation appearing in indium antimonide infrared focal-plane arrays (InSb IRFPAs) subjected to the thermal shock tests, results in the fracturing of the InSb chip, which restricts its final yield. In light of the proposed three-dimensional modeling, we proposed the method of thinning a silicon readout integrated circuit (ROIC) to level the uneven top surface of InSb IRFPAs. Simulation results show that when the silicon ROIC is thinned from 300 μm to 20 μm, the maximal displacement in the InSb IRFPAs linearly decreases from 7.115 μm to 0.670 μm in the upward direction, and also decreases linearly from 14.013 μm to 1.612 μm in the downward direction. Once the thickness of the silicon ROIC is less than 50 μm, the square checkerboard buckling deformation distribution presenting in the thicker InSb IRFPAs disappears, and the top surface of the InSb IRFPAs becomes flat. All these findings imply that the thickness of the silicon ROIC determines the degree of deformation in the InSb IRFPAs under a thermal shock test, that the method of thinning a silicon ROIC is suitable for decreasing the fracture probability of the InSb chip, and that this approach improves the reliability of InSb IRFPAs.

Carbon Nanotube Gas Sensor Fabricated on Anodic Aluminum Oxide

2007 ◽  
Vol 124-126 ◽  
pp. 1309-1312
Author(s):  
Nguyen Duc Hoa ◽  
Nguyen Van Quy ◽  
Gyu Seok Choi ◽  
You Suk Cho ◽  
Se Young Jeong ◽  
...  
Keyword(s):  
Carbon Nanotubes ◽  
Carbon Nanotube ◽  
Gas Sensor ◽  
Chemical Vapor ◽  
Fast Response ◽  
Device Fabrication ◽  
Alumina Oxide ◽  
Response And Recovery ◽  
New Type ◽  
P Type

A new type of gas sensor was realized by directly depositing carbon nanotube on nano channels of the anodic alumina oxide (AAO) fabricated on p-type silicon substrate. The carbon nanotubes were synthesized by thermal chemical vapor deposition at a very high temperature of 1200 oC to improve the crystallinity. The device fabrication process was also developed. The contact of carbon nanotubes and p-type Si substrate showed a Schottky behavior, and the Schottky barrier height increased with exposure to gases while the overall conductivity decreased. The sensors showed fast response and recovery to ammonia gas upon the filling (400 mTorr) and evacuation.

scholarly journals E/D-Mode GaN Inverter on a 150-mm Si Wafer Based on p-GaN Gate E-Mode HEMT Technology

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 617
Author(s):  
Li-Fang Jia ◽  
Lian Zhang ◽  
Jin-Ping Xiao ◽  
Zhe Cheng ◽  
De-Feng Lin ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Room Temperature ◽  
Supply Voltage ◽  
High Input ◽  
Smart Power ◽  
Input Noise ◽  
Power Integrated Circuit ◽  
Different Temperatures ◽  
Device Technology ◽  
Si Wafer

AlGaN/GaN E/D-mode GaN inverters are successfully fabricated on a 150-mm Si wafer. P-GaN gate technology is applied to be compatible with the commercial E-mode GaN power device technology platform and a systematic study of E/D-mode GaN inverters has been conducted with detail. The key electrical characters have been analyzed from room temperature (RT) to 200 °C. Small variations of the inverters are observed at different temperatures. The logic swing voltage of 2.91 V and 2.89 V are observed at RT and 200 °C at a supply voltage of 3 V. Correspondingly, low/high input noise margins of 0.78 V/1.67 V and 0.68 V/1.72 V are observed at RT and 200 °C. The inverters also demonstrate small rising edge time of the output signal. The results show great potential for GaN smart power integrated circuit (IC) application.

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