scholarly journals A Theoretical Modeling Analysis of Adapted Composite CNT Bundle for High-Speed VLSI Interconnect

2021 ◽  
Author(s):  
Abu Bony Amin ◽  
S M Shakil ◽  
Muhammad Sana Ullah
Keyword(s):  
Carbon Nanotube ◽  
Behavioral Change ◽  
High Speed ◽  
Large Scale ◽  
Propagation Delay ◽  
Global Level ◽  
Modeling Analysis ◽  
Large Scale Integration ◽  
To Come ◽  
Scale Integration

The aroused quest to reduce the delay at interconnect level is the main urge of this paper to come across a configuration of Carbon Nanotube (CNT) bundle namely squarely packed bundle of composite CNTs. The approach, demonstrated in this paper, adapts the composite bundle to adopt for high speed Very Large Scale Integration (VLSI) interconnect with technology sizing down. To reduce the delay of the proposed configuration of composite CNT bundle, the behavioral change of Resistance (R), Inductance (L) and Capacitance (C) has been observed with respect to both width of the bundle and diameter of the CNTs in the bundle. Consequently, the performance of the modified bundle configuration is compared with previously developed configuration namely squarely packed bundle of dimorphic MWCNTs in terms of propagation delay and crosstalk delay at local, semiglobal and global level interconnect. The proposed bundle configuration is ultimately enacted as better one for 32nmand 16nmtechnology node and suitable for 7nmas well.

scholarly journals Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method

2021 ◽  
Vol 9 (VI) ◽  
pp. 962-966
Author(s):  
Ayush Tiwari
Keyword(s):  
Large Scale ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Time Duration ◽  
Leakage Reduction ◽  
Large Scale Integration ◽  
Cmos Vlsi ◽  
Scale Integration

Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits based on CMOS. For this research paper, a technique called Advance Leakage reduction (AL reduction) is proposed to reduce the leakage power in CMOS logic circuits. To draw our structure circuit related to CMOS like Inverter, inverted AND, and NOR etc. we have seen the power and delay for circuits. This paper incorporates, analyzing of several minimization techniques as compared with proposed work to illustrate minimization in ratio of energy and time usage and time duration for propagation. LECTOR, Source biasing, Stack ONOFIC method is observed and analyzed with the proposed method to evaluate the leakage power consumption and propagation delay for logic circuits based on CMOS. Entire work has done in LT Spice Software with 180nm library of CMOS.

Multi-Layer Ceramic Packaging for High Frequency Mixed-Signal VLSI ASICS

2009 ◽  
Vol 6 (1) ◽  
pp. 38-41
Author(s):  
Lewis Dove
Keyword(s):  
Integrated Circuits ◽  
High Frequency ◽  
High Speed ◽  
Large Scale ◽  
Flip Chip ◽  
Data Converters ◽  
Mixed Signal ◽  
Large Scale Integration ◽  
Circuit Techniques ◽  
Scale Integration

Mixed-signal Application Specific Integrated Circuits (ASICs) have traditionally been used in test and measurement applications for a variety of functions such as data converters, pin electronics circuitry, drivers, and receivers. Over the past several years, the complexity, power density, and bandwidth of these chips has increased dramatically. This has necessitated dramatic changes in the way these chips have been packaged. As the chips have become true VLSI (Very Large Scale Integration) ICs, the number of I/Os have become too large to interconnect with wire bonds. Thus, it has become necessary to utilize flip chip interconnects. Also, the bandwidth of the high-speed signal paths and clocks has increased into the multi Gbit or GHz ranges. This requires the use of packages with good high-frequency performance which are designed using microwave circuit techniques to optimize signal integrity and to minimize signal crosstalk and noise.

Energy-Aware Switch Design

2013 ◽  
pp. 341-360 ◽  
Author(s):  
Yukihiro Nakagawa ◽  
Takeshi Shimizu ◽  
Takeshi Horie ◽  
Yoichi Koyanagi ◽  
Osamu Shiraki ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Single Chip ◽  
Energy Aware ◽  
It Industry ◽  
Gigabit Ethernet ◽  
Switch Architecture ◽  
Large Scale Integration ◽  
Scale Integration

The use of virtualization technology has been increasing in the IT industry to consolidate servers and reduce power consumption significantly. Virtualized commodity servers are scaled out in the data center and increase the demand for bandwidth between servers. Therefore, a high performance switch is required. The shared-memory switch is the best performance/cost switch architecture, but it is challenging to satisfy the requirements on the memory bandwidth in a high speed network. In addition, it is challenging to handle variable-length frames in Ethernet. This chapter describes the main challenges in Ethernet switch designs and then energy-aware switch designs, including switch architecture and high speed IO interface. As implementation examples, this chapter also describes a single-chip switch Large Scale Integration (LSI) embedded with high-speed IO interfaces and 10-Gigabit Ethernet (10GbE) switch blade equipped with the switch LSI. The switch blade delivers 100% more performance per watt than other 10GbE switch blades in the industry.

Porous low dielectric constant materials for microelectronics

2005 ◽  
Vol 364 (1838) ◽  
pp. 201-215 ◽  
Author(s):  
Mikhail R Baklanov ◽  
Karen Maex
Keyword(s):  
Dielectric Constant ◽  
High Speed ◽  
Large Scale ◽  
Low Dielectric Constant ◽  
Low Dielectric ◽  
Large Scale Integration ◽  
The Subject ◽  
On Chip ◽  
Scale Integration ◽  
Selection Of

Materials with a low dielectric constant are required as interlayer dielectrics for the on-chip interconnection of ultra-large-scale integration devices to provide high speed, low dynamic power dissipation and low cross-talk noise. The selection of chemical compounds with low polarizability and the introduction of porosity result in a reduced dielectric constant. Integration of such materials into microelectronic circuits, however, poses a number of challenges, as the materials must meet strict requirements in terms of properties and reliability. These issues are the subject of the present paper.

Large-Scale Integration: What Is Yet to Come?

Science ◽  
1977 ◽  
Vol 195 (4283) ◽  
pp. 1102-1106 ◽  
Author(s):  
R. N. Noyce
Keyword(s):  
Large Scale ◽  
Large Scale Integration ◽  
To Come ◽  
Scale Integration

Self-Aligned Growth and Optimization of Carbon Nanotube

2011 ◽  
Vol 179-180 ◽  
pp. 316-319
Author(s):  
Ying Wu ◽  
Zhao Ying Zhou ◽  
Li Jun Sun ◽  
Jin Zhang ◽  
Xiao Yun Zhang
Keyword(s):  
Carbon Nanotube ◽  
Large Scale ◽  
Gas Flow ◽  
Flow Direction ◽  
Parallel Method ◽  
Sem Images ◽  
Sensing Systems ◽  
Aligned Growth ◽  
Large Scale Integration ◽  
Scale Integration

CNT-based integrated components show potential application in many fields. The growth of carbon nanotube is very important process for the fabrication of CNT-based component. Self-aligned growth of carbon nanotube method by gas-flowing techniques is reported in this paper, which results in CNT growth along gas-flow direction. The effect of gas-flow was analyzed with numerical simulation and the growth optimization was put forward. Scanning electronic microscopy (SEM) images demonstrate that the self-aligned carbon nanotube can be realized by a gas-flowing CVD process and the distribution of carbon nanotube can be controlled by the gas-flowing rates. This research provides a parallel method for the large-scale integration of carbon nanotube into electronic, optoelectronic, and sensing systems.

VLSI Implementation and Software Co-Simulation of Digital Image Watermarking with Increased Security

2020 ◽  
Vol 10 (4) ◽  
pp. 634-638
Author(s):  
Vardhana M. ◽  
Anil Kumar Bhat
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
Large Scale ◽  
Image Watermarking ◽  
Intensity Level ◽  
Performance Parameters ◽  
Security Measures ◽  
Large Scale Integration ◽  
And Performance ◽  
Scale Integration

Background: Security is one of the fundamental and essential factors, which has to be addressed in the field of communication. Communication refers to the exchange of useful information between two or more nodes. Sometimes it is required to exchange some of the confidential information such as a company’s logo, which needs to be hidden from the third person. The data that is being exchanged between these nodes has to be kept confidential and secured from unintended users. The three fundamental components of security are confidentiality, integrity and authentication. The data that is being exchanged has to be confidential, and only the authorized party should have access to the information that is being exchanged. One of the key methods for securing the data is encryption. Objective: The main objective of this paper was to address the problem of data hiding and security in communication systems. There is a need for having hardware resources for having high speed data security and protection. Methods: In this paper, we implemented image watermarking using LSB technique to hide a secret image, and employed encryption using Advanced Encryption Standard, to enhance the security of the image. An image is a two dimensional signal, with each pixel value representing the intensity level. The secure transmission of the image along the channel is a challenging task, because of the reason that, any individual can access it, if no security measures are taken. Conclusion: An efficient method of digital watermarking has been implemented with increased security and performance parameters are presented. Results: In this paper, hardware realization of image watermarking/encryption and dewatermarking/ decryption is implemented using Very Large Scale Integration. The design is verified by means of co-simulation using MATLAB and Xilinx. The paper also presents the performance parameters of the design, with respect to speed, area and power.

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