scholarly journals sboxgates: A program for finding low gate count implementations of S-boxes

2021 ◽  
Vol 6 (62) ◽  
pp. 2946
Author(s):  
Marcus Dansarie
Keyword(s):  
Gate Count

scholarly journals Determining Gate Count Reliability in a Library Setting

2016 ◽  
Vol 11 (3) ◽  
pp. 68
Author(s):  
Jeffrey Phillips
Keyword(s):  
Heavy Traffic ◽  
Academic Library ◽  
Data Set ◽  
Statistical Software ◽  
Card Reader ◽  
University Library ◽  
Library Assessment ◽  
Gate Count ◽  
Counter Data

Objective – Patron counts are a common form of measurement for library assessment. To develop accurate library statistics, it is necessary to determine any differences between various counting devices. A yearlong comparison between card reader turnstiles and laser gate counters in a university library sought to offer a standard percentage of variance and provide suggestions to increase the precision of counts. Methods – The collection of library exit counts identified the differences between turnstile and laser gate counter data. Statistical software helped to eliminate any inaccuracies in the collection of turnstile data, allowing this data set to be the base for comparison. Collection intervals were randomly determined and demonstrated periods of slow, average, and heavy traffic. Results – After analyzing 1,039,766 patron visits throughout a year, the final totals only showed a difference of .43% (.0043) between the two devices. The majority of collection periods did not exceed a difference of 3% between the counting instruments. Conclusion – Turnstiles card readers and laser gate counters provide similar levels of reliability when measuring patron activity. Each system has potential counting inaccuracies, but several methods exist to create more precise totals. Turnstile card readers are capable of offering greater detail involving patron identity, but their high cost makes them inaccessible for libraries with lower budgets. This makes laser gate counters an affordable alternative for reliable patron counting in an academic library.

scholarly journals A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box

2013 ◽  
Vol 2013 ◽  
pp. 1-26 ◽  
Author(s):  
Jia Hao Kong ◽  
Li-Minn Ang ◽  
Kah Phooi Seng
Keyword(s):  
Computer Architecture ◽  
Nonlinear Property ◽  
Set Partitioning ◽  
Advanced Encryption Standard ◽  
Instruction Set ◽  
Selective Encryption ◽  
Low Area ◽  
Gate Count ◽  
Hierarchical Trees ◽  
Spiht Algorithm

The “S-box” algorithm is a key component in the Advanced Encryption Standard (AES) due to its nonlinear property. Various implementation approaches have been researched and discussed meeting stringent application goals (such as low power, high throughput, low area), but the ultimate goal for many researchers is to find a compact and small hardware footprint for the S-box circuit. In this paper, we present our version of minimized S-box with two separate proposals and improvements in the overall gate count. The compact S-box is adopted with a compact and optimum processor architecture specifically tailored for the AES, namely, the compact instruction set architecture (CISA). To further justify and strengthen the purpose of the compact crypto-processor’s application, we have also presented a selective encryption architecture (SEA) which incorporates the CISA as a part of the encryption core, accompanied by the set partitioning in hierarchical trees (SPIHT) algorithm as a complete selective encryption system.

Design of Efficient Reversible BCD Adder–Subtractor Architecture and Its Optimization Using Carry Skip Logic

2016 ◽  
Vol 25 (07) ◽  
pp. 1650076 ◽  
Author(s):  
Praveena Murugesan ◽  
Thanushkodi Keppanagounder ◽  
Vijeyakumar Natarajan
Keyword(s):  
Critical Role ◽  
Optical Computing ◽  
Complementary Metal Oxide Semiconductor ◽  
Deep Submicron ◽  
Reversible Logic ◽  
Oxide Semiconductor ◽  
Single Digit ◽  
Gate Count ◽  
Ripple Carry Adder ◽  
Novel Design

In the present era, reversible logic designs play a very critical role in nanotechnology, low power complementary metal-oxide semiconductor (CMOS) designs, optical computing and, especially, in quantum computing. High power dissipation and leakage current in deep submicron technologies is a severe threat in applications created today. As a consequence, design of datapath elements in reversible logic has gained much importance. In this study, a novel design of binary coded decimal (BCD) adder/subtractor in reversible logic has been proposed. As a further optimization of the proposed reversible decimal design, carry skip (CSK) logic is used for reversible ripple carry adder stages. This reduces delay but at the expense of little hardware. The proposed BCD adder/subtractor and its optimized version are designed using structural VHDL and simulated using ModelSim 6.3f. Performance analysis reveals that the proposed BCD design demonstrates reductions in gate count, garbage outputs and constant inputs of 30.5%, 46% and 28%, respectively, and its optimized version exhibits 19.4%, 32.4% and 16% reductions in gate count, garbage outputs and constant inputs compared to the design in Ref. 14 [V. Rajmohan, V. Renganathan and M. Rajmohan, A novel reversible design of unified single digit BCD adder–subtractor, Int. J. Comput. Theor. Eng. 3 (2011) 697–700].

scholarly journals Synthesis of composite logic gate in QCA embedding underlying regular clocking

2021 ◽  
Vol 34 (1) ◽  
pp. 115-131
Author(s):  
Jayanta Pal ◽  
Dhrubajyoti Bhowmik ◽  
Ayush Singh ◽  
Apu Saha ◽  
Bibhash Sen
Keyword(s):  
Symmetric Functions ◽  
Logic Gate ◽  
Logic Gates ◽  
Cmos Technology ◽  
Dissipated Energy ◽  
Circuit Realization ◽  
Alternative Technologies ◽  
Gate Count ◽  
Majority Voter ◽  
Cost Efficient

Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative technologies for current CMOS technology. It has the advantage of computing at a faster speed, consuming lower power, and work at Nano- Scale. Besides these advantages, QCA logic is limited to its primitive gates, majority voter and inverter only, results in limitation of cost-efficient logic circuit realization. Numerous designs have been proposed to realize various intricate logic gates in QCA at the penalty of non-uniform clocking and improper layout. This paper proposes a Composite Gate (CG) in QCA, which realizes all the essential digital logic gates such as AND, NAND, Inverter, OR, NOR, and exclusive gates like XOR and XNOR. Reportedly, the proposed design is the first of its kind to generate all basic logic in a single unit. The most striking feature of this work is the augmentation of the underlying clocking circuit with the logic block, making it a more realistic circuit. The Reliable, Efficient, and Scalable (RES) underlying regular clocking scheme is utilized to enhance the proposed design?s scalability and efficiency. The relevance of the proposed design is best cited with coplanar implementation of 2-input symmetric functions, achieving 33% gain in gate count and without any garbage output. The evaluation and analysis of dissipated energy for both the design have been carried out. The end product is verified using the QCADesigner2.0.3 simulator, and QCAPro is employed for the study of power dissipation.

scholarly journals Exponentially faster implementations of Select(H) for fermionic Hamiltonians

Quantum ◽  
2021 ◽  
Vol 5 ◽  
pp. 380
Author(s):  
Kianna Wan
Keyword(s):  
Quantum Chemistry ◽  
General Framework ◽  
State Of The Art ◽  
Quantum Algorithms ◽  
Condensed Matter ◽  
Quantum Circuits ◽  
Constant Independent ◽  
Wigner Transform ◽  
Gate Count ◽  
Hamiltonian Simulation

We present a simple but general framework for constructing quantum circuits that implement the multiply-controlled unitary Select(H):=∑ℓ|ℓ⟩⟨ℓ|⊗Hℓ, where H=∑ℓHℓ is the Jordan-Wigner transform of an arbitrary second-quantised fermionic Hamiltonian. Select(H) is one of the main subroutines of several quantum algorithms, including state-of-the-art techniques for Hamiltonian simulation. If each term in the second-quantised Hamiltonian involves at most k spin-orbitals and k is a constant independent of the total number of spin-orbitals n (as is the case for the majority of quantum chemistry and condensed matter models considered in the literature, for which k is typically 2 or 4), our implementation of Select(H) requires no ancilla qubits and uses O(n) Clifford+T gates, with the Clifford gates applied in O(log2n) layers and the T gates in O(logn) layers. This achieves an exponential improvement in both Clifford- and T-depth over previous work, while maintaining linear gate count and reducing the number of ancillae to zero.

scholarly journals Writing on the walls: Engaging students through whiteboards

2017 ◽  
Vol 78 (5) ◽  
pp. 255 ◽  
Author(s):  
Karen Pruneda ◽  
Amber Wilson ◽  
Jessica Riedmueller
Keyword(s):  
Physical Space ◽  
Faculty Members ◽  
Fiscal Year ◽  
Digital Environment ◽  
Carnegie Classification ◽  
Staff Members ◽  
Gate Count ◽  
Master's Colleges And Universities ◽  
Student Workers ◽  
The University

In today’s digital environment, connecting with students in a meaningful way can be difficult. Our recent whiteboard project at the University of Central Arkansas (UCA) was a successful way for us to engage students in the physical space of the library. UCA’s Carnegie classification is “Master’s Colleges and Universities (larger programs)” and had a total enrollment of 11,487 students for the fall 2016 semester. For the fiscal year 2015–16 our gate count was 482,934 students. The UCA Library operations are managed by 11 faculty members and 30 staff members, plus the assistance of 35 student workers.

scholarly journals Understanding the Impact of Street Patterns on Pedestrian Distribution: A Case Study in Tianjin, China

2021 ◽  
Author(s):  
Qiang Sheng ◽  
Junfeng Jiao ◽  
Tianyu Pang
Keyword(s):  
Base Layer ◽  
City Center ◽  
Street Pattern ◽  
Gate Count ◽  
A Minor ◽  
The Impact ◽  
The City ◽  
Street Segments ◽  
Urban Functions

AbstractThis paper investigates the impact of street pattern, metro stations, and density of urban functions on pedestrian distribution in Tianjin, China. Thirteen neighborhoods are selected from the city center and suburbs. Pedestrian and vehicle volumes are observed through detailed gate count from 703 street segments in these neighborhoods. Regression models are constructed to analyze the impact of the street pattern, points of interest (POIs), and vehicle and metro accessibility on pedestrian volumes in each neighborhood and across the city. The results show that when analyzing all neighborhoods together, local street connectivity and POIs had a strong influence on pedestrian distribution. Proximity to metro stations and vehicle accessibility had a minor impact. When analyzing each neighborhood separately, both local- and city-scale street patterns affect pedestrian distributions. These findings suggest that the street pattern provides a base layer for metro stations to attract both the emergence of active urban functions and pedestrian movement.

scholarly journals Performance Analysis Of Secured Synchronous Stream Ciphers

2011 ◽  
pp. 22-26
Author(s):  
Padmalatha Eddla ◽  
R.Ravinder Reddy
Keyword(s):  
Information And Communication Technologies ◽  
Data Encryption ◽  
Stream Ciphers ◽  
Divide And Conquer ◽  
Clock Frequency ◽  
Sensitive Data ◽  
Good Efficiency ◽  
Digital Storage ◽  
Gate Count ◽  
Correlation Attacks

The new information and communication technologies require adequate security. In the past decades ,we have witnessed an explosive growth of the digital storage and communication of data ,triggered by some important breakthroughs such as the Internet and the expansive growth of wireless communications. In the world of cryptography ,stream ciphers are known as primitives used to ensure privacy over communication channel and these are widely used for fast encryption of sensitive data. Lots of old stream ciphers that have been formerly used no longer be considered secure ,because of their vulnerability to newly developed cryptanalysis techniques. Many designs stream ciphers have been proposed in an effort to find a proper candidate to be chosen as world standard for data encryption. From these designs, the stream ciphers which are Trivium,Edon80 and Mickey are implemented in ‘c’ language with out affecting their security .Actually these algorithms are particularly suited for hardware oriented environments which provides considerable security and efficiency aspects. We will be targeting hardware applications, and good measure for efficiency of a stream cipher in this environment is the number of key stream bits generated per cycle per gate. For good efficiency we are approaching two ways .One approach is minimizing the number of gates.The other approach is to dramatically increase the number of bits for cycle. This allows reducing the clock frequency at the cost of an increased gate count. Apart from the implementation the analysis which includes the security of these algorithms against some attacks related to stream ciphers such as guess and deterministic attacks, correlation attacks, divide and conquer attacks and algebraic attacks are presented.

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