scholarly journals Synthesis of composite logic gate in QCA embedding underlying regular clocking

2021 ◽  
Vol 34 (1) ◽  
pp. 115-131
Author(s):  
Jayanta Pal ◽  
Dhrubajyoti Bhowmik ◽  
Ayush Singh ◽  
Apu Saha ◽  
Bibhash Sen
Keyword(s):  
Symmetric Functions ◽  
Logic Gate ◽  
Logic Gates ◽  
Cmos Technology ◽  
Dissipated Energy ◽  
Circuit Realization ◽  
Alternative Technologies ◽  
Gate Count ◽  
Majority Voter ◽  
Cost Efficient

Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative technologies for current CMOS technology. It has the advantage of computing at a faster speed, consuming lower power, and work at Nano- Scale. Besides these advantages, QCA logic is limited to its primitive gates, majority voter and inverter only, results in limitation of cost-efficient logic circuit realization. Numerous designs have been proposed to realize various intricate logic gates in QCA at the penalty of non-uniform clocking and improper layout. This paper proposes a Composite Gate (CG) in QCA, which realizes all the essential digital logic gates such as AND, NAND, Inverter, OR, NOR, and exclusive gates like XOR and XNOR. Reportedly, the proposed design is the first of its kind to generate all basic logic in a single unit. The most striking feature of this work is the augmentation of the underlying clocking circuit with the logic block, making it a more realistic circuit. The Reliable, Efficient, and Scalable (RES) underlying regular clocking scheme is utilized to enhance the proposed design?s scalability and efficiency. The relevance of the proposed design is best cited with coplanar implementation of 2-input symmetric functions, achieving 33% gain in gate count and without any garbage output. The evaluation and analysis of dissipated energy for both the design have been carried out. The end product is verified using the QCADesigner2.0.3 simulator, and QCAPro is employed for the study of power dissipation.

CHARACTERIZATION, TEST AND LOGIC SYNTHESIS OF NOVEL CONSERVATIVE AND REVERSIBLE LOGIC GATES FOR QCA

2010 ◽  
Vol 09 (03) ◽  
pp. 201-214 ◽  
Author(s):  
KUNAL DAS ◽  
DEBASHIS DE
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Symmetric Functions ◽  
Logic Gate ◽  
Logic Synthesis ◽  
Vlsi Design ◽  
Logic Gates ◽  
Reversible Logic ◽  
Computing Paradigm ◽  
Scale Integration

Quantum dot cellular automaton (QCA) is an emerging technology in the field of nanotechnology. Reversible logic is emerging as a promising computing paradigm with applications in low-power quantum computing and QCA in the field of very large scale integration (VLSI) design. In this paper, we worked on conservative logic gate (CLG) and reversible logic gate (RLG). We examined that RLG and CLG are two classes of logic family intersecting each other. The intersection of RLG and CLG is parity preserving reversible (PPR) or conservative reversible logic gate (CRLG). We proposed in this paper, three algorithms to find different k × k RLG as well as CLG. Here, we demonstrate only the most promising two proposed gates of different categories. We compared the results with that of the previous Fredkin gate. The result shows that logic synthesis using above two gates will be a promising step towards the low-power QCA design era. We have shown a parity preserving approach to design all possible CLG. We also discuss a coupled Majority–minority-Voter (MmV) in a single nanostructure, dual outputs are driven simultaneously. This MmV gate is used for implementing n variables symmetric functions, testing the conservative gates as we explained that parity must be preserved if Majority and Minority output are same as input as well as output of CLG.

scholarly journals Dynamic power dissipation of basic logic gates

2021 ◽  
Author(s):  
Katayoun Pourbahri
Keyword(s):  
Power Dissipation ◽  
Logic Gate ◽  
Load Condition ◽  
Order Relation ◽  
Logic Gates ◽  
Cmos Technology ◽  
Output Coupling ◽  
Basic Logic ◽  
Dynamic Power ◽  
Proposed Model

In this thesis, a model is proposed to estimate the dynamic power dissipation of CMOS logic gate that is loaded with identical logic gates. The proposed model is based on parsitic capacitance, input capacitance and input-to-output coupling capacitance of the gate. Also, model takes into account transistor width and has a second order relation with fanout. Using 0.13um CMOS technology and netlist (Cadence), basic logic gates are designed and loaded by identical basic logic gates. Basic logic gates dynamic power are simulated and compared with the calculated values of proposed model over a range of transistor sizes and capacitive load condition. The proposed model shows a good agreement with the simulated value of dynamic power dissipation of basic logic gates that are loaded by identical basic logic gates.

Testable Novel Parity-Preserving Reversible Gate and Low-Cost Quantum Decoder Design in 1D Molecular-QCA

2017 ◽  
Vol 26 (09) ◽  
pp. 1750145 ◽  
Author(s):  
Neeraj Kumar Misra ◽  
Bibhash Sen ◽  
Subodh Wairya ◽  
Bandan Bhoi
Keyword(s):  
Circuit Design ◽  
Low Cost ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Quantum Cost ◽  
Gate Count ◽  
Reversible Gate ◽  
Majority Voter ◽  
Decoder Design ◽  
Decoder Circuit

In this era of emerging technology, reversible logic is applied for circuit design. Due to the deep submicron and scaling, a number of pitfalls are faced by the CMOS technology. So a lot of constraints related to CMOS are stated with the QCA technology. The aim of this paper is the efficient conservative reversible decoder circuit design with optimal reversible metrics. It aims at furnishing a proposed DC gate (DC stands for decoder comparator) to help the construction of these mentioned circuits. Finally, the DC is employed to construct the [Formula: see text]-bit reversible decoder. Moreover, a new concept of the quantum equivalent of combined reversible gates is presented by the algorithm. By the comparative outcomes, it is found that the proposed decoder had achieved 25% quantum cost, 66% gate count, and 50% garbage outputs as compared to the counterpart. Further, stuck-at-fault for the single- and multiple-bit input and output is applied to the DC gate for testability. Moreover, the DC gate in the physical foreground on QCADesigner achieved 0.63 μm2 area, 15 majority voter gates, and 451 cell complexities. It is observed that nanoelectronics has also made an inevitable contribution in the area of QCA.

scholarly journals Dynamic power dissipation of basic logic gates

2021 ◽  
Author(s):  
Katayoun Pourbahri
Keyword(s):  
Power Dissipation ◽  
Logic Gate ◽  
Load Condition ◽  
Order Relation ◽  
Logic Gates ◽  
Cmos Technology ◽  
Output Coupling ◽  
Basic Logic ◽  
Dynamic Power ◽  
Proposed Model

In this thesis, a model is proposed to estimate the dynamic power dissipation of CMOS logic gate that is loaded with identical logic gates. The proposed model is based on parsitic capacitance, input capacitance and input-to-output coupling capacitance of the gate. Also, model takes into account transistor width and has a second order relation with fanout. Using 0.13um CMOS technology and netlist (Cadence), basic logic gates are designed and loaded by identical basic logic gates. Basic logic gates dynamic power are simulated and compared with the calculated values of proposed model over a range of transistor sizes and capacitive load condition. The proposed model shows a good agreement with the simulated value of dynamic power dissipation of basic logic gates that are loaded by identical basic logic gates.

scholarly journals Design and Implementation of New Coplanar FA Circuits without NOT Gate and Based on Quantum-Dot Cellular Automata Technology

2021 ◽  
Vol 11 (24) ◽  
pp. 12157
Author(s):  
Mohsen Vahabi ◽  
Pavel Lyakhov ◽  
Ali Newaz Bahar ◽  
Khan A. Wahid
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Logic Gate ◽  
Logic Gates ◽  
Full Adder ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Xor Gate ◽  
Design Complexity ◽  
Quantum Dot Cellular Automata

The miniaturization of electronic devices and the inefficiency of CMOS technology due to the development of integrated circuits and its lack of responsiveness at the nanoscale have led to the acquisition of nanoscale technologies. Among these technologies, quantum-dot cellular automata (QCA) is considered one of the possible replacements for CMOS technology because of its extraordinary advantages, such as higher speed, smaller area, and ultra-low power consumption. In arithmetic and comparative circuits, XOR logic is widely used. The construction of arithmetic logic circuits using AND, OR, and NOT logic gates has a higher design complexity. However, XOR gate design has a lower design complexity. Hence, the efficient and optimized XOR logic gate is very important. In this article, we proposed a new XOR gate based on cell-level methodology, with the expected output achieved by the influence of the cells on each other; this design method caused less delay. However, this design was implemented without the use of inverter gates and crossovers, as well as rotating cells. Using the proposed XOR gate, two new full adder (FA) circuits were designed. The simulation results indicate the advantage of the proposed designs compared with previous structures.

A STUDY ON DIVERSE NANOSTRUCTURE FOR IMPLEMENTING LOGIC GATE DESIGN FOR QCA

2011 ◽  
Vol 10 (01n02) ◽  
pp. 263-269 ◽  
Author(s):  
KUNAL DAS ◽  
DEBASHIS DE
Keyword(s):  
High Speed ◽  
Logic Gate ◽  
Logic Synthesis ◽  
Cmos Technology ◽  
Effective Area ◽  
Defect Tolerance ◽  
Efficient Design ◽  
Voltage Level ◽  
Majority Voter ◽  
Speed Computer

Quantum dot cellular automata (QCA) define the nanostructure of basic computer. It is used as an alternative for designing high-speed computer over CMOS technology. The basic logic in QCA is the logic state that does not measure with voltage level; rather it measures the polarity of electrons in cell. The Majority Voter (MV) is first introduced to design the logic circuits, but only using MV, designing complex logic circuit became inefficient. Many proposals had been made for designing QCA logic gate. In this paper we focus on different useful nanostructures, reduced size and efficient design of Nand–Nor Inverter (NNI), 3 × 3 tile structures for implementing NNI, And–Or Logic, and AOI also present logic synthesis using proposed gates. We analyze QCA defect on proposed gates and describe its permissible defect tolerance. In QCA we describe application for implementing standard functions using proposed structures in this paper and describe effective area of proposed structures.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

Recent advances in molecular logic gate chemosensors based on luminescent metal organic frameworks

2021 ◽  
Author(s):  
Bei Li ◽  
Dongsheng Zhao ◽  
Feng Wang ◽  
Xiaoxian Zhang ◽  
Wenqian Li ◽  
...  
Keyword(s):  
Logic Gate ◽  
Metal Organic Frameworks ◽  
Logic Gates ◽  
Design Strategies ◽  
Molecular Logic Gate ◽  
Future Developments ◽  
Molecular Logic ◽  
Molecular Logic Gates ◽  
Recent Advances ◽  
Metal Organic

This review covers the latest advancements of molecular logic gates based on LMOF. The classification, design strategies, related sensing mechanisms, future developments, and challenges of LMOFs-based logic gates are discussed.

Power–Delay-Error-Efficient Approximate Adder for Error-Resilient Applications

2019 ◽  
Vol 28 (10) ◽  
pp. 1950171 ◽  
Author(s):  
Vinay Kumar ◽  
Ankit Singh ◽  
Shubham Upadhyay ◽  
Binod Kumar
Keyword(s):  
Image Processing ◽  
Power Consumption ◽  
Logic Gate ◽  
Logic Gates ◽  
Error Tolerance ◽  
Approximate Computing ◽  
Processing Application ◽  
Error Resilient ◽  
Delay Performance ◽  
Prime Concern

Power dissipation has been the prime concern for CMOS circuits. Approximate computing is a potential solution for addressing this concern as it reduces power consumption resulting in improved performance in terms of power–delay product (PDP). Decrease of power consumption in approximate computing is achieved by approximating the demand of accuracy as per the error tolerance of the system. This paper presents a new approach for designing approximate adder by introducing inexactness in the existing logic gate(s). Approximated logic gates provide flexibility in designing low power error-resilient systems depending on the error tolerance of the applications such as image processing and data mining. The proposed approximate adder (PAA) has higher accuracy than existing approximate adders with normalized mean error distance of 0.123 and 0.1256 for 16-bit and 32-bit adder, respectively, and lower PDP of 1.924E[Formula: see text]18[Formula: see text]J for 16-bit adder and 5.808E[Formula: see text]18[Formula: see text]J for 32-bit adder. The PAA also performs better than some of the recent approximate adders reported in literature in terms of layout area and delay. Performance of PAA has also been evaluated with an image processing application.

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