scholarly journals Comparative Analysis of Different Figures of Merit for Algan/Gan and Si Surrounding-Gate Field Effect Transistors (SG-Fets)

Author(s):  
Yogesh Kumar Verma ◽  
Varun Mishra ◽  
Manoj Singh Adhikari ◽  
Dharam Buddhi ◽  
Santosh Kumar Gupta

Abstract The combination of better transport properties of III-V group semiconductors along with excellent electrostatic control of surrounding gate is a promising option for the future low power electronics. Accordingly in this brief, the major figures of merit (FOM) including output current, output conductance (gd), transconductance generation factor (TGF), intrinsic gain (dB), and dynamic power dissipation are computed for surrounding-gate field effect transistors (SG-FETs) considering III-V group semiconductors and Si channel material respectively with respect to different device parameters. It is noticed that the center potential is higher in AlGaN/GaN SG-FET than Si for different values of channel length (CL), channel height (H), oxide thickness (tox), and doping concentration (Nd). The AlGaN/GaN SG-FET provides lower gd than Si for different values of CL, H, tox, and Nd as required for MOS analog circuits to achieve higher gain. The peak value of TGF and intrinsic gain is higher in AlGaN/GaN than Si SG-FET for different values of CL, H, tox, and Nd. In this work, we have analyzed the MOSFET structure for normally off operation of AlGaN/GaN high electron mobility transistors (HEMTs) to reduce dynamic power dissipation (PD). The magnitude of PD is calculated to be lower in normally off AlGaN/GaN SG-FET than Si for different values of CL, H, and tox.

2020 ◽  
Vol 15 (1) ◽  
pp. 1-18 ◽  
Author(s):  
Yogesh Kumar Verma ◽  
Varun Mishra ◽  
Santosh Kumar Gupta

In this work, analog and linearity distortion performance of a III–V AlGaN/GaN quadruple gate field effect transistor (III–V QG-FET) has been analyzed and compared with conventional Si QG-FET having identical physical dimensions. Specifically, we investigate the linearity by numerically computing transconductance (gm1), its second and third order derivatives (gm2 and gm3), along-with linearity metrics comprising of third order intermodulation distortion (IMD3), third order input intercept point (IIP3), and extrapolated input voltages (VIP2 and VIP3). The consequences of variations in physical parameters of III–V QG-FET, i.e., channel length, channel height, the thickness of oxide layer, doping concentration, along-with temperature on the linearity metrics parameters, drain current, and threshold voltage are analyzed and compared with Si QG-FET. The gate capacitance and dynamic power dissipation is calculated numerically and compared by performing small signal AC analysis at 1 MHz frequency for III–V and Si QG-FETs. The influence of variations in above mentioned physical parameters is also analyzed on dynamic power dissipation and gate capacitance considering the effects of quantum capacitance in the nanometer regime. The present analysis reveals that in III–V QG-FET, the dynamic power dissipation is considerably reduced than its contender Si QG-FET due to its reduced threshold voltage, and thus it is a more promising candidate for analog and low power dissipation applications.


Silicon ◽  
2021 ◽  
Author(s):  
Yogesh Kumar Verma ◽  
Varun Mishra ◽  
Manoj Singh Adhikari ◽  
Dharam Buddhi ◽  
Santosh Kumar Gupta

2011 ◽  
Vol 4 (6) ◽  
pp. 064201 ◽  
Author(s):  
Tomonori Nishimura ◽  
Choong Hyun Lee ◽  
Toshiyuki Tabata ◽  
Sheng Kai Wang ◽  
Kosuke Nagashio ◽  
...  

Author(s):  
Vijay Kumar Sharma

Carbon nanotube field effect transistors (CNTFETs) are the best alternative option for the metal oxide semiconductor field effect transistor (MOSFET) in the ultra-deep submicron (ultra-DSM) regime. CNTFET has numerous benefits such as lower off-state current, high current density, low bias potential and better transport property as compared to MOSFET. A rolled graphene sheet-based cylindrical tube is constructed in the channel region of the CNTFET structure. In this paper, an improved domino logic (IDL) configuration is proposed for domino logic circuits to improve the different performance metrics. An extensive comparative simulation analysis is provided for the different performance metrics for different circuits to verify the novelty of the proposed IDL approach. The IDL approach saves the leakage power dissipation by 95.61% and enhances the speed by 87.10% for the 4-bit full adder circuit as compared to the best reported available domino method. The effects of the number of carbon nanotubes (CNTs), temperature, and power supply voltage variations are estimated for leakage power dissipation for the 16-input OR (OR16) gate. The reliability of different performance metrics for different circuit is calculated in terms of uncertainty by running the Monte Carlo simulations for 500 samples. Stanford University’s 32[Formula: see text]nm CNTFET model is applied for circuit simulations.


2012 ◽  
Vol 101 (25) ◽  
pp. 253511 ◽  
Author(s):  
Y. G. Xiao ◽  
Z. J. Chen ◽  
M. H. Tang ◽  
Z. H. Tang ◽  
S. A. Yan ◽  
...  

2003 ◽  
Vol 200 (1) ◽  
pp. 168-174 ◽  
Author(s):  
Narihiko Maeda ◽  
Takehiko Tawara ◽  
Tadashi Saitoh ◽  
Kotaro Tsubaki ◽  
Naoki Kobayashi

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