Reliability and Power Analysis of FinFET Based SRAM

Mapping Intimacies ◽

10.21203/rs.3.rs-759064/v1 ◽

2021 ◽

Author(s):

Alluri Navaneetha ◽

K. Bikshalu

Keyword(s):

Power Dissipation ◽

Power Analysis ◽

High Reliability ◽

Standard Test ◽

Single Chip ◽

Short Channel ◽

Technology Roadmap ◽

Low Leakage ◽

Channel Effects ◽

Low Power Dissipation

Abstract Demand for accommodating more and new functionalities within a single chip such as SOC needs a novel devices and architecture such as FinFET device instead of MOSFET. FinFET is emerged as non-planar, multigate device to overcome short channel effects such as subthreshold swing deterioration, drain induced barrier lowering, threshold voltage roll off which degrade circuit performance. As the need of device technology is mounting in electronic gadgets the important parameters are taken into consideration such as low leakage, high reliability, low power dissipation, and high operating speed. Reliability is one of key considerations in converting a proof of concept into reality. In this work Reliability of FinFET device is studied experimentally according to ITRS (international technology roadmap for semiconductor) roadmap using several standard test protocols such as multiple current stressing, harsher environment conditions, and effect of electromigration. Furthermore, power analysis of FinFET based SRAM is done by using 7nm bsimcmg PTM files in mentor graphics tool. The FinFET based SRAM shown low leakage, power dissipation, delay compared to existing conventional MOSFET based SRAM.

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InP/InGaAs DHBTs Technology for Single-Chip 20-Gbit/s Regenerative Receiver Circuits with Extremely Low Power Dissipation

Ultrafast Electronics and Optoelectronics ◽

10.1364/ueo.1997.ud4 ◽

1997 ◽

Author(s):

Shoji Yamahata ◽

Kenji Kurishima ◽

Hiroki Nakajima ◽

Eiichi Sano

Keyword(s):

Low Power ◽

Power Dissipation ◽

Single Chip ◽

Low Power Dissipation

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The Research of Embedded Techniques in Control Systems of Service Robots

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.219-220.214 ◽

2011 ◽

Vol 219-220 ◽

pp. 214-218

Author(s):

Lian Jun Hu ◽

Hong Song ◽

Xiao Hui Zeng ◽

Wei Li

Keyword(s):

Control System ◽

Low Power ◽

Control Systems ◽

Power Dissipation ◽

High Reliability ◽

Service Robots ◽

Arm Processor ◽

Entire Structure ◽

Low Power Dissipation ◽

Hard Real Time

A control system for service robots based on a 32-bit ARM processor with kernel S3C2410 is proposed. The entire structure of the control system of embedded service robots is designed in the paper. And designs of each circuit and software of the system are demonstrated respectively in detail. The control system proposed has advantages of modularized structure, small size, low power dissipation, hard real-time and high reliability, etc.

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Studying Technology of Collaborative Virtual Prototyping of Louver under ADAMS Platform

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.33.204 ◽

2010 ◽

Vol 33 ◽

pp. 204-207

Author(s):

Feng Chen Liu ◽

Lan Yu Yang

Keyword(s):

Power Dissipation ◽

Simple Structure ◽

Characteristic Property ◽

High Reliability ◽

Virtual Prototyping ◽

Thermal Control ◽

Design Stage ◽

Low Power Dissipation ◽

Structure Light ◽

Controlled Object

As a kind of active thermal-control technology, emissivity of the radiation surface greatly can be changed effectively by electric thermal-control louver, the heat exchange of the internal and external of the satellite can be adjusted, then heat-transfer characteristics of the controlled object could be adjusted timely, it reacts to the external change flexibly and precision of the thermoregulation is high. Model of louver was built r by ADAMS, then model of virtual prototyping was built during the system design stage and simulation of electromechanical joint was carried out by making use of both ADAMS and Matlab. Machinery characteristic property of system was derived from ADAMS, and joint simulation was realized by Simulink module of Matlab. Results indicates that machinery component of the louver can satisfy the technology index request completely, and has some characteristics such as simple structure, light weight, low power dissipation and high reliability.

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Transient Annealing of Boron Implanted Devices

MRS Proceedings ◽

10.1557/proc-23-279 ◽

1983 ◽

Vol 23 ◽

Cited By ~ 1

Author(s):

S. R. Wilson ◽

W. M. Paulson ◽

C. J. Varker ◽

A. Lowe ◽

R. B. Gregory ◽

...

Keyword(s):

Bipolar Transistors ◽

Ring Oscillators ◽

Short Channel Effects ◽

Leakage Currents ◽

Short Channel ◽

Low Leakage ◽

Channel Effects ◽

Recombination Lifetimes ◽

Implanted Devices ◽

Temperature Furnace

ABSTRACTShallow-junction semiconductor devices have been fabricated using ion implantation and transient annealing with a Varian IA-200 isothermal annealer. Boron implanted diodes, npn bipolar transistors and CMOS ring oscillators have been fabricated and are compared to furnace annealed devices. Boron implanted diodes have been annealed with the RIA and yield acceptably low leakage currents, comparable to furnace annealed devices. The RIA devices have recombination lifetimes of ∼10 μsec. The bipolar transistors subjected to a transient anneal have good base-collector and emitterbase junctions as well as gains of ∼100 in good agreement with the design of the device. MOSFETs and CMOS ring oscillators were fabricated using self-aligned polysilicon gates. The transient annealed devices were equal or superior to devices which were furnace annealed at 800°C for 10 min. The low temperature furnace anneal was necessary to minimize short channel effects. The transient anneal resulted in ring oscillators which were a factor of two faster than furnace samples that were annealed.

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100-nm Channel Length a-Si:H Vertical Thin Film Transistors

MRS Proceedings ◽

10.1557/proc-814-i2.4/a3.4 ◽

2004 ◽

Vol 814 ◽

Author(s):

Isaac Chan ◽

Arokia Nathan

Keyword(s):

Thin Film ◽

Thin Film Transistors ◽

Vertical Channel ◽

Channel Length ◽

Channel Structure ◽

Large Area ◽

Short Channel ◽

Low Leakage ◽

Low Leakage Current ◽

Channel Effects

AbstractThis paper reports on hydrogenated amorphous silicon (a-Si:H) vertical thin film transistors (VTFTs) with channel length of 100 nm, using conventional planar TFT processing technology. The device has a fully self-aligned vertical channel structure, which is highly insensitive to the non-uniformity of reactive ion etching (RIE). Therefore, the VTFT process is very suitable for large-area electronics. Presently, we can demonstrate VTFTs with remarkable ON/OFF current ratio of more than 108, low leakage current down to 1 fA, and good subthreshold slope of 0.8 V/dec at Vd = 1.5 V. The impacts of contemporary device issues, such as short-channel effects and contact resistance, on the performance of short-channel VTFTs and suggested avenues for improvement are discussed.

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Secondary Ion Mass Spectrometry For The Year 2000 and Beyond: Are There Any Showstoppers?

Microscopy and Microanalysis ◽

10.1017/s1431927600011272 ◽

1997 ◽

Vol 3 (S2) ◽

pp. 877-878

Author(s):

Charles W. Magee

Keyword(s):

Mass Spectrometry ◽

Secondary Ion Mass Spectrometry ◽

Short Channel ◽

Technology Roadmap ◽

Ion Mass Spectrometry ◽

Channel Effects ◽

Measured Profile ◽

Atomic Mixing ◽

Year 2000 ◽

Secondary Ion

The National Technology Roadmap of Semiconductors (NTRS) shows that future semiconductor processing will require the formation of junctions less than 30nm deep with gate lengths approaching, and becoming less than, 0.lum. Techniques must be available to measure these in-depth, as well as spatial, distributions.Secondary ion mass spectrometry (SIMS) has long been the technique of choice for measuring dopant profiles in semiconductors. The depth of the junctions formed has, up top now, always been sufficiently deep into the semiconductor that the effects of the analysis on the measured profile (i.e. atomic mixing) could be ignored for the most part. In addition, gate lengths have been sufficiently large that diffusion of LDD implants under the gate have not contributed significantly to short-channel effects. However, the relentless decrease in the required junction depths and gate lengths may mean that the situation may change in the near future.

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Characterization of Sub 130 Nanometer Gate Length SOI MOSFET Devices Exhibiting Short Channel Effects

ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2003p0478 ◽

2003 ◽

Author(s):

Terence Kane ◽

Michael P. Tenney ◽

John Bruley

Keyword(s):

Electrical Characterization ◽

Short Channel Effects ◽

Line Edge Roughness ◽

Short Channel ◽

Critical Dimensions ◽

Technology Roadmap ◽

Transmission Electron ◽

Edge Roughness ◽

Channel Effects

Abstract As MOSFET device gate lengths shrink below the 130 nanometer node, the effects of short channel effects (SCE) and gate line edge roughness (LER) have an increasingly more pronounced affect on device performance [1-8, 10]. The 2001 International Technology Roadmap for Semiconductors (ITRS) predicts increasingly tighter critical dimensions (CD) control limits on LER from 2.7 nm in 2004 to 1.3 nm in 2010 [9,11]. As gate lengths shrink, resist etch processes emerge as the most significant contributor to LER [1-8, 11]. In addition, another contributing factor to SCE is junction implant defects. Examples of gate LER effects and junction defects in 130 nanometer node SOI SRAM MOSFET devices identified by sub-micron electrical characterization with analysis by high resolution transmission electron microscopy (TEM) are discussed.

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Design and Analysis of N-Type CNTFET Based 2 X 1 Multiplexer

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.229-231.1656 ◽

2012 ◽

Vol 229-231 ◽

pp. 1656-1661 ◽

Cited By ~ 1

Author(s):

Y. Varthamanan ◽

V. Kannan

Keyword(s):

Power Dissipation ◽

Power Analysis ◽

Operating Voltage ◽

Resistive Load ◽

Efficient Design ◽

Short Channel ◽

Channel Effect ◽

Promising Application ◽

Carbon Nano Tube ◽

Efficient Power

This paper enumerates the efficient design and analysis of N-type CNTFET based 2X1 Multiplexer. The Multiplexer is designed using Ballistic CNTFET (VHDL-AMS model) with the dcnt of 1nm in resistive load inverter logic. The transient and power analysis are obtained with operating voltage at 0.6V for the multiplexer using system vision tool. There are many issues facing while integrating many number of transistors like short channel effect, power dissipation, scaling of the transistors. To overcome these problems by Consider the carbon nano tube(CNT) have promising application in the field of electronics. The simulation results are presented, and the power consumptions are compared with the conventional MOSFET design. The comparison of results indicated that the CNTFET based design is capable of efficient power savings.

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