Characterization of Sub 130 Nanometer Gate Length SOI MOSFET Devices Exhibiting Short Channel Effects

2003 ◽  
Author(s):  
Terence Kane ◽  
Michael P. Tenney ◽  
John Bruley
Keyword(s):  
Electrical Characterization ◽  
Short Channel Effects ◽  
Line Edge Roughness ◽  
Short Channel ◽  
Critical Dimensions ◽  
Technology Roadmap ◽  
Transmission Electron ◽  
Edge Roughness ◽  
Channel Effects

Abstract As MOSFET device gate lengths shrink below the 130 nanometer node, the effects of short channel effects (SCE) and gate line edge roughness (LER) have an increasingly more pronounced affect on device performance [1-8, 10]. The 2001 International Technology Roadmap for Semiconductors (ITRS) predicts increasingly tighter critical dimensions (CD) control limits on LER from 2.7 nm in 2004 to 1.3 nm in 2010 [9,11]. As gate lengths shrink, resist etch processes emerge as the most significant contributor to LER [1-8, 11]. In addition, another contributing factor to SCE is junction implant defects. Examples of gate LER effects and junction defects in 130 nanometer node SOI SRAM MOSFET devices identified by sub-micron electrical characterization with analysis by high resolution transmission electron microscopy (TEM) are discussed.

50nm Gate-Length Hydrogen Terminated Diamond Field Effect Transistors – Characterization and Inspection of Operation.

2011 ◽  
Vol 1282 ◽  
Author(s):  
David A. J. Moran ◽  
Donald A. MacLaren ◽  
Samuele Porro ◽  
Richard Hill ◽  
Helen McLelland ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Gate Length ◽  
Short Channel Effects ◽  
Short Channel ◽  
Transmission Electron ◽  
Channel Effects ◽  
Physical And Chemical ◽  
Electron Energy Loss

ABSTRACTHydrogen terminated diamond field effect transistors (FET) of 50nm gate length have been fabricated, their DC operation characterised and their physical and chemical structure inspected by Transmission Electron Microscopy (TEM) and Electron Energy Loss Spectroscopy (EELS). DC characterisation of devices demonstrated pinch-off of the source-drain current can be maintained by the 50nm gate under low bias conditions. At larger bias, off-state output conductance increases, demonstrating most likely the onset of short-channel effects at this reduced gate length.

scholarly journals Design and software characterization of finFET based full adders

2019 ◽  
Vol 8 (1) ◽  
pp. 51
Author(s):  
Raju Hajare ◽  
C. Lakshminarayana
Keyword(s):  
Field Effect Transistors ◽  
Full Adder ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Switching Speed ◽  
Chip Area ◽  
Channel Effects ◽  
Technology Nodes

Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and 16T 1-bit full adders at various  technology nodes using HSPICE software. Results show that FinFET based full adder design gives better performance in terms of speed, power and reliability compared to MOSFET based full adder designs. Hence FinFET are promising candidates and better replacement for MOSFET.

scholarly journals Design and characterization of a 10 nm finfet

2019 ◽  
Vol 15 (4) ◽  
pp. 609-612
Author(s):  
Kim Ho Yeap ◽  
Jun Yi Lee ◽  
Wei Long Yeo ◽  
Humaira Nisar ◽  
Siu Hong Loh
Keyword(s):  
Leakage Current ◽  
Short Channel Effects ◽  
Short Channel ◽  
Drive Current ◽  
Design Specifications ◽  
Transfer Characteristics ◽  
Channel Effects ◽  
Output Characteristics

This paper presents the design, characterization, and analysis of a 10 nm silicon negative channel FinFET. To validate the design, we have simulated the output characteristics and transfer characteristics of the transistor. Both of which comply with the standard characteristics of an operational MOSFET. Owing to its efficacy in suppressing short channel effects, the leakage current of the tri-gate transistor is found to be low; whereas, the drive current is sufficiently high. We have also presented the design specifications of the transistor.

Monte Carlo study of 50 nm-long single and dual-gate MODFETs: suppression of short-channel effects

1993 ◽  
Vol 3 (9) ◽  
pp. 1719-1728
Author(s):  
P. Dollfus ◽  
P. Hesto ◽  
S. Galdin ◽  
C. Brisset
Keyword(s):  
Monte Carlo ◽  
Monte Carlo Study ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
Dual Gate

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

Sign in / Sign up

Export Citation Format

Share Document